KR960027253A - Operational Amplifier Circuit - Google Patents

Operational Amplifier Circuit Download PDF

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Publication number
KR960027253A
KR960027253A KR1019940040494A KR19940040494A KR960027253A KR 960027253 A KR960027253 A KR 960027253A KR 1019940040494 A KR1019940040494 A KR 1019940040494A KR 19940040494 A KR19940040494 A KR 19940040494A KR 960027253 A KR960027253 A KR 960027253A
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KR
South Korea
Prior art keywords
signal
differential
amplification
amplifying
generate
Prior art date
Application number
KR1019940040494A
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Korean (ko)
Inventor
백경일
Original Assignee
곽정소
한국전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 곽정소, 한국전자 주식회사 filed Critical 곽정소
Priority to KR1019940040494A priority Critical patent/KR960027253A/en
Publication of KR960027253A publication Critical patent/KR960027253A/en

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Abstract

본 발명의 목적은 반도체 칩의 크기를 증대시키지 않고, 한개의 연산 증폭기 소자로서 두 신호의 차신호 및 합신호를 하나의 신호로 변환하여 궤한에 따라 연산처리할 수 있는 연신 증폭회로에 관한 것으로, 이와같은 본 발명의 목적을 달성하기 위한 수단은 두쌍의 차동 입력단자로부터 각각 신호를 수신하여 그 차신호를 발생시키기 위해 각각 차동증폭을 행하는 2개의 차동 증폭수단과, 상기 2개의 차동 증폭수단에 의해 각각 증폭된 두 차신호를 수신하여 이 두 신호를 합하는 회로 수단과, 상기 합하는 회로수단에 합해진 신호를 수신하여 충분히 큰 신호를 발생시키기 위해 충분히 큰 증폭도를 가지고 증폭을 행하는 증폭 회로 수단을 포함하는 것을 특징으로 한다.SUMMARY OF THE INVENTION An object of the present invention relates to a stretch amplification circuit capable of converting a difference signal and a sum signal of two signals into a single signal and performing arithmetic processing according to the error, without increasing the size of the semiconductor chip. Means for achieving the object of the present invention comprises two differential amplification means for receiving a signal from each of the two differential input terminals and performing differential amplification to generate the difference signal, respectively, by the two differential amplification means Circuit means for receiving each amplified difference signal and combining the two signals and amplifying circuit means for amplifying with a sufficiently large amplification degree to receive a signal combined with the summation circuit means and generate a sufficiently large signal. It features.

Description

연산증폭회로Operational Amplifier Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도의 (가)는 본 발명에 따른 두 신호의 차 및 합신호를 하나의 신하나의 신호로 변환하는 연산증폭기의 등가회로도와 그 심볼, 제4도의 (나)는 종래의 연산증폭기의 등가회로도와 그 심볼, 제5도의 (가)는 본 발명에 따른 연산증폭기를 이용하여 두 신호의 차신호를 하나의 신호로 변환, 연산하는 하이임피던스 연산증폭회로, 제5도는 (나)는 본 발명에 따른 연산증폭기를 이용하여 두신호의 합신호를 하나의 신호로 변환, 연산하는 하이임피던스 연산증폭회로, 제5도의 (다)는 종래의 연산증폭기를 이용하여 하나의 신호를 연산하는 하이임피던스 연산증폭회로.4A is an equivalent circuit diagram of an operational amplifier for converting a difference and a sum signal of two signals according to the present invention into one new one signal, and a symbol thereof, and FIG. 4B is an equivalent circuit diagram of a conventional operational amplifier. Figure 5 (a) is a high impedance operational amplifier circuit for converting and calculating the difference signal of two signals into one signal using the operational amplifier according to the present invention, Figure 5 is (b) in the present invention A high impedance operational amplifier circuit for converting and calculating the sum signal of two signals into a single signal using the operational amplifier according to FIG. 5, (C) of FIG. 5 shows a high impedance operational amplifier for calculating a single signal using a conventional operational amplifier. Circuit.

Claims (1)

두쌍의 차동 입력단자로부터 각각 신호를 수신하여 그 차신호를 발생시키기 위해 각각 차동증폭을 행하는 2개의 차동 증폭수단과, 상기 2개의 차동 증폭수단에 의해 각각 증폭된 두 차신호를 수신하여 이 두 신호를 합하는 회로 수단과, 상기 합하는 회로수단에서 합해진 신호를 수신하여 충분히 큰 신호를 발생시키기 위해 충분히 큰 증폭도를 가지고 증폭을 행하는 증폭회로 수단을 포함하는 것을 특징으로 하는 연산증폭회로.Two differential amplification means each receiving a signal from two pairs of differential input terminals and performing differential amplification to generate the difference signal, and two differential signals amplified by the two differential amplifying means respectively. And amplifying circuit means for amplifying with a sufficiently large amplification degree to receive a sum signal from the summating circuit means and generate a sufficiently large signal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940040494A 1994-12-31 1994-12-31 Operational Amplifier Circuit KR960027253A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940040494A KR960027253A (en) 1994-12-31 1994-12-31 Operational Amplifier Circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940040494A KR960027253A (en) 1994-12-31 1994-12-31 Operational Amplifier Circuit

Publications (1)

Publication Number Publication Date
KR960027253A true KR960027253A (en) 1996-07-22

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ID=66648145

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940040494A KR960027253A (en) 1994-12-31 1994-12-31 Operational Amplifier Circuit

Country Status (1)

Country Link
KR (1) KR960027253A (en)

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