KR960026066A - Single Crystal Silicon-on-Insulator Wafer Manufacturing Method - Google Patents

Single Crystal Silicon-on-Insulator Wafer Manufacturing Method Download PDF

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Publication number
KR960026066A
KR960026066A KR1019940032792A KR19940032792A KR960026066A KR 960026066 A KR960026066 A KR 960026066A KR 1019940032792 A KR1019940032792 A KR 1019940032792A KR 19940032792 A KR19940032792 A KR 19940032792A KR 960026066 A KR960026066 A KR 960026066A
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South Korea
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silicon
layer
silicon wafer
wafer
forming
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KR1019940032792A
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Korean (ko)
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KR0171067B1 (en
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이석수
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문정환
Lg 반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

본 발명은 다공질 실리콘을 이용하여 단결정 SOI(Silicon-on-Insulator) 웨이퍼를 제조하는 방법으로써, 1) 제1실리콘 웨이퍼에 소정부분 다공질 실리콘층을 형성하는 단계와, 2)다공징 실리콘층 위에 실리콘 에피텍셜층을 형성하는 단계와, 3) 제1실리콘 웨이퍼의 에피텍셜층 상과 제2실리콘 웨이퍼 상에 각각 산화막층을 형성하는 단계와, 4) 제1실리콘 웨이퍼와, 제2실리콘 웨이퍼를 각각의 산화막층을 맞대어 본딩하는 단계와, 6)어닐링하는 단계와, 7)제1실리콘 웨이퍼의 실리콘층을 제거하는 단계와, 8)제1실리콘 웨이퍼의 다공질 실리콘층을 선택적으로 식각 제거하는 단계와, 9)수소(hydrogen) 분위기에서 어닐링하는 단계를 포함하여 이루어진다.The present invention is a method for manufacturing a single crystal silicon-on-insulator (SOI) wafer using porous silicon, comprising the steps of: 1) forming a predetermined portion of a porous silicon layer on a first silicon wafer, and 2) silicon on the porous silicon layer. Forming an epitaxial layer, 3) forming an oxide layer on the epitaxial layer and the second silicon wafer of the first silicon wafer, and 4) forming the first silicon wafer and the second silicon wafer, respectively. Bonding the oxide layer of the metal oxide layer to each other, 6) annealing, 7) removing the silicon layer of the first silicon wafer, 8) selectively etching away the porous silicon layer of the first silicon wafer, and 9) annealing in a hydrogen atmosphere.

Description

단결정 SOI(Silicon-on-Insulator) 웨이퍼 제조방법Single Crystal Silicon-on-Insulator Wafer Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 단결정 SOI 웨이퍼 제조방법을 설명하기 위해 웨이퍼의 일부 단면을 도시한 단면도.2 is a cross-sectional view showing a partial cross section of a wafer for explaining the method of manufacturing a single crystal SOI wafer of the present invention.

Claims (8)

단결정 SOI(Silicon-on-Insulator) 웨이퍼를 제조하는 방법에 있어서, 1)제1실리콘 웨이퍼에 소정부분 다공질 실리콘층을 형성하는 단계와, 2) 상기 다공질 실리콘층 위에 실리콘 에피텍셜층을 형성하는 단계와, 3) 상기 제1실리콘 웨이퍼의 에피텍셜층 상에 산화막층을 형성하고, 제2실리콘 웨이퍼 상에 산화막층을 형성하는 단계와, 4)상기 제1실리콘 웨이퍼와, 제2실리콘 웨이퍼를 각각의 산화막층을 맞대어 본딩하는 단계와, 6)어닐링하는 단계와, 7)상기 제1실리콘 웨이퍼의 실리콘층을 제거하는 단계와, 8) 상기 제1실리콘 웨이퍼의 다공질 실리콘층을 선택적으로 식각 제거하는 단계와, 9)수소 분위기에서 어닐링하는 단계를 포함하여 이루어진 단결정 SOI 웨이퍼 제조방법.A method of manufacturing a single crystal silicon-on-insulator (SOI) wafer, comprising the steps of: 1) forming a portion of a porous silicon layer on a first silicon wafer, and 2) forming a silicon epitaxial layer on the porous silicon layer. And 3) forming an oxide layer on the epitaxial layer of the first silicon wafer, and forming an oxide layer on the second silicon wafer, and 4) the first silicon wafer and the second silicon wafer, respectively. Bonding the oxide layers of the silicon oxide layer to each other, 6) annealing, 7) removing the silicon layer of the first silicon wafer, and 8) selectively etching away the porous silicon layer of the first silicon wafer. And 9) annealing in a hydrogen atmosphere. 제1항에 있어서, 상기 1)단계에서 제1실리콘 웨이퍼는 P-불순물이 확산된 실리콘 웨이퍼인 것을 특징으로 하는 단결정 SOI 웨이퍼 제조방법.The method of claim 1, wherein the first silicon wafer in step 1) is a silicon wafer in which P − impurities are diffused. 제1항에 있어서, 상기 1)단계에서 다공질실리콘층의 형성은 HF 양극반응시켜 형성하는 것을 특징으로 하는 단결정 SOI 웨이퍼 제조방법.The method of claim 1, wherein the porous silicon layer is formed by HF anodic reaction in the step 1). 제3항에 있어서, 상기 HF은 15 내지 48wt% HF인 것을 특징으로 하는 단결정 SOI 웨이퍼 제조방법.The method of claim 3, wherein the HF is from 15 wt% to 48 wt% HF. 제1항에 있어서, 상기 6)단계의 어닐링은 약 1200℃, 약 5분간 실행하는 것을 특징으로 하는 단결정 SOI 웨이퍼 제조방법.The method of claim 1, wherein the annealing of step 6) is performed at about 1200 ° C. for about 5 minutes. 제1항에 있어서, 상기 7)단계에서 실리콘층의 제거는 연마하여 제거하는 것을 특징으로 하는 단결정 SOI 웨이퍼 제조방법.The method of claim 1, wherein the removal of the silicon layer in step 7) is performed by grinding. 제1항에 있어서, 상기 8)단계에서 다공질 실리콘층의 선택적 식각 제거는 48wt% HF; 30wt% H2O2용액을 1:5의 부피비로 하여 상온에서 식각 제거함을 특징으로 하는 단결정 SOI 웨이퍼 제조방법.The method of claim 1, wherein the selective etching removal of the porous silicon layer in step 8) is 48wt% HF; A method of manufacturing a single crystal SOI wafer, wherein the 30 wt% H 2 O 2 solution is etched away at room temperature in a volume ratio of 1: 5. 제1항에 있어서, 상기 9)단계에서 어닐링하는 약 1150℃ 온도와, 약 80Torr 압력에서 약 1시간동안 실행하는 것을 특징으로 하는 단결정 SOI 웨이퍼 제조방법.10. The method of claim 1 wherein said annealing is performed at about < RTI ID = 0.0 > 1150 C < / RTI > and about 80 Torr pressure for about 1 hour. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940032792A 1994-12-05 1994-12-05 Method of manufacturing silicon-on-insulator wafer KR0171067B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100363124B1 (en) * 1997-12-26 2003-01-24 캐논 가부시끼가이샤 Substrate processing method and apparatus and soi substrate
KR100371450B1 (en) * 1999-02-02 2003-02-06 캐논 가부시끼가이샤 Substrate and method of manufacturing the same

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100476901B1 (en) * 2002-05-22 2005-03-17 삼성전자주식회사 Method of forming SOI(Silicon-On-Insulator) semiconductor substrate
KR102677831B1 (en) 2019-03-13 2024-06-24 주식회사 엘지화학 Method for manufacturing silicon wafer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100363124B1 (en) * 1997-12-26 2003-01-24 캐논 가부시끼가이샤 Substrate processing method and apparatus and soi substrate
KR100371450B1 (en) * 1999-02-02 2003-02-06 캐논 가부시끼가이샤 Substrate and method of manufacturing the same
US6624047B1 (en) 1999-02-02 2003-09-23 Canon Kabushiki Kaisha Substrate and method of manufacturing the same

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