KR960025071A - Dual Channel Direct Memory Access (DMA) Transfer Method - Google Patents

Dual Channel Direct Memory Access (DMA) Transfer Method Download PDF

Info

Publication number
KR960025071A
KR960025071A KR1019940040186A KR19940040186A KR960025071A KR 960025071 A KR960025071 A KR 960025071A KR 1019940040186 A KR1019940040186 A KR 1019940040186A KR 19940040186 A KR19940040186 A KR 19940040186A KR 960025071 A KR960025071 A KR 960025071A
Authority
KR
South Korea
Prior art keywords
dma
transfer
data
full
memory access
Prior art date
Application number
KR1019940040186A
Other languages
Korean (ko)
Inventor
노병철
Original Assignee
구자홍
Lg 전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 구자홍, Lg 전자 주식회사 filed Critical 구자홍
Priority to KR1019940040186A priority Critical patent/KR960025071A/en
Publication of KR960025071A publication Critical patent/KR960025071A/en

Links

Landscapes

  • Bus Control (AREA)

Abstract

본 발명은 DMA 기능을 수행하는 채널을 복수개 구비함으로써 단일 채널 전송시보다 데이타 전송율을 향상 시키고자 한 이중 채널 직접 메모리 액세스(DMA)의 전송방법에 관한 것이다.The present invention relates to a method for transmitting a dual channel direct memory access (DMA) to improve the data rate compared to a single channel transmission by providing a plurality of channels performing a DMA function.

종래의 DMA 전송방법은 단일 채널에 의한 것이어서 DMA 전송시의 데이터 전송율이 저하되는 문제점이 있었다.The conventional DMA transfer method is a single channel, which causes a problem that the data transfer rate during DMA transfer is lowered.

이를 개선코자하여 본 발명은 DMA 기능을 수행하는 채널을 복수개로 구비하고 상호 독립적인 전송을 수행함으로써 데이타 전송율을 기존의 방식에 비하여 최대 2배까지 향상시킴으로써 시스템의 성능 향상을 도모코자 한 것이다.In order to improve this, the present invention is intended to improve the performance of the system by improving the data rate by up to 2 times compared to the conventional method by providing a plurality of channels performing the DMA function and performing independent transmission.

Description

이중 채널 직접 메모리 액세스(DMA) 전송 방법Dual Channel Direct Memory Access (DMA) Transfer Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 이중 채널 DMA 전송 방법을 설명하는 플로우 챠트.2 is a flow chart illustrating a dual channel DMA transfer method according to the present invention.

Claims (1)

DMA에 필요한 값들을 초기화 한 상태에서 DMA 전송을 시작하여 전송하고자 하는 데이타를 소오스에서 읽어 들어고(Src-full A) 읽어들인 데이타를 전송시키기 위해 임시 저장한 후 상태(dest-full A) 버스상으로 데이타를 전송하고 데이타 전송이 완료 되었으면 카운트 값들을 증감시킨 후 재차 소오스에서 전송하고자 하는 데이타들을 읽어들이는 상태(src-full A)로 리턴해서 데이타 카순트값이 ψ가 되면 DMA 전송을 종료하는 A채널의 1과정과, A 채널에서 전송하고자 하는 데이타를 소오스에서 읽어 들인 상태(src-full A)가 되면 카운트값들을 증감시키고 별도로 소오스에서 데이타를 읽어 들이고(src-full B) 읽어 들인 데이타를 전송시키기 위해 임시 저장한 후(dest-full B) 버스상으로 데이타를 전송하고 전송이 완료되면 다시 카운트 값을 증감시키는 상태로 리턴하고, 데이타 카운트값이 ψ가 되면 곧바로 DMA 전송을 종료하는 B 채널의 제2과정으로 이루어짐을 특징으로 하는 이중 채널 직접 메모리 액세스(DMA) 전송 방법.Start the DMA transfer with the necessary values for the DMA, and start the DMA transfer to read the data to be transferred (Src-full A) and temporarily store it for transfer. After the data transfer is completed, if the data transfer is completed, increase or decrease the count value and return to the state (src-full A) that reads the data to be transmitted from the source again. When the data count is ψ, A ends the DMA transfer. When the first process of the channel and the data to be transmitted on the A channel are read from the source (src-full A), the count values are increased or decreased, and the data is read separately from the source (src-full B) and the read data is transmitted. After the temporary storage (dest-full B) to transfer the data on the bus and returns to the state of increasing or decreasing the count value when the transfer is complete, A second step transfer method dual-channel direct memory access (DMA), characterized by constituted by any of the B-channel to directly terminate the DMA transfer when the count value of the itaconic ψ. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940040186A 1994-12-30 1994-12-30 Dual Channel Direct Memory Access (DMA) Transfer Method KR960025071A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940040186A KR960025071A (en) 1994-12-30 1994-12-30 Dual Channel Direct Memory Access (DMA) Transfer Method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940040186A KR960025071A (en) 1994-12-30 1994-12-30 Dual Channel Direct Memory Access (DMA) Transfer Method

Publications (1)

Publication Number Publication Date
KR960025071A true KR960025071A (en) 1996-07-20

Family

ID=66648076

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940040186A KR960025071A (en) 1994-12-30 1994-12-30 Dual Channel Direct Memory Access (DMA) Transfer Method

Country Status (1)

Country Link
KR (1) KR960025071A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100726361B1 (en) * 2005-06-30 2007-06-11 시그마텔, 인크. System and method for communicating with memory devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100726361B1 (en) * 2005-06-30 2007-06-11 시그마텔, 인크. System and method for communicating with memory devices

Similar Documents

Publication Publication Date Title
KR880004380A (en) Bus master with burst transfer mode
HK1018342A1 (en) High performance universal multi-port internally cached dynamic random access memory system, architecture and method
DE69516577D1 (en) Data bus communication
AU2003213840A1 (en) Memory system with burst length shorter than prefetch length
KR850008017A (en) CMOS input / output circuit
SE9603862D0 (en) Device and method for calculating FFT
DE60039375D1 (en) Transmission system with dynamic priority scheme
WO2003044652A3 (en) High-speed first-in-first-out buffer
KR930020903A (en) Byte tracking system and method
KR890005739A (en) Bus master with selected delay burst
KR960025071A (en) Dual Channel Direct Memory Access (DMA) Transfer Method
KR950012223A (en) How to prevent decryption of encrypted computer purpose codes
UA42887C2 (en) Control chart for nonvolatile semiconductor storage unit
JPS5762432A (en) Input and output system
KR100242992B1 (en) Readout prohibition system of program rom
TW247948B (en) Network card
KR970060790A (en) How to transfer bit blocks of data
KR950024079A (en) Data bus width converter
JPS57105019A (en) Data transfer controlling system
KR960027836A (en) Overhead Reduction Method in Fast Packet Transmission
KR100303320B1 (en) Fourier Converter
KR960039670A (en) Viterbi decoding method using specified status
KR950024049A (en) How to Improve Driving Performance of Terminal Controller Devices
KR910001570A (en) Bus method for controlling multiple slaves
JPH0646083A (en) Buffer memory circuit

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application