KR960025033A - Data transmission / reception circuit for communication between processors - Google Patents

Data transmission / reception circuit for communication between processors Download PDF

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Publication number
KR960025033A
KR960025033A KR1019940038102A KR19940038102A KR960025033A KR 960025033 A KR960025033 A KR 960025033A KR 1019940038102 A KR1019940038102 A KR 1019940038102A KR 19940038102 A KR19940038102 A KR 19940038102A KR 960025033 A KR960025033 A KR 960025033A
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South Korea
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signal
control signal
terminal
response
data
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KR1019940038102A
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Korean (ko)
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KR0185600B1 (en
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박용우
공준진
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김광호
삼성전자 주식회사
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1072—Decentralised address translation, e.g. in distributed shared memory systems

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)

Abstract

1. 청구범위에 기재된 발명이 속하는 기술 분야 : 프로세서간의 데이터 통신을 효율적으로 할 수 있도록 램을 이용하여구현된 데이터 통신회로에 관한 것이다.The technical field to which the invention described in the claims pertains relates to a data communication circuit implemented using a RAM to efficiently perform data communication between processors.

2. 발명에 해결하려고 하는 기술적 과제 : 램을 이용하여 데이터를 전송하되, 전송완료후 전송된 데이터의 사이즈를 나타내는 사이즈 데이터를 우선 송신-수신하여 데이터의 송수신을 행하는 회로를 제공한다.2. Technical problem to be solved by the invention: Provides a circuit which transmits and receives data by transmitting data by using a RAM and first transmitting and receiving size data indicating the size of the transmitted data after completion of the transmission.

3. 발명의 해결방법의 요지 : 송신측의 프로세서에서 전송하고자하는 데이터를 메모리에 기록한 후, 전송된 데이터의 사이즈를 나타내는 데이터를 사이즈 레지스터에 기록한다. 수신측의 프로세서는 상기 사이즈 레지스터의 출력을 먼저 읽어수신될 데이터의 사이즈를 먼저 검출한후 상기 메모리로부터 해당하는 사이즈의 데이터를 읽어 들이어 상호간에 데이터통신을 수행한다. 이때, 본 발명에서는 메모리의 이용을 배타적으로 하기 위한 송신제어신호와 송신준비신호를 상호간에송수신하는 회로를 더 구비한다.3. Summary of Solution of the Invention: After writing the data to be transmitted by the processor on the sending side into the memory, the data indicating the size of the transferred data is written into the size register. The processor on the receiving side first reads the size of the output of the size register, detects the size of the data to be received, and then reads data of the corresponding size from the memory to perform data communication with each other. At this time, the present invention further includes a circuit for transmitting and receiving a transmission control signal and a transmission ready signal for exclusive use of the memory.

4. 발명의 중요한 용도 : 프로세서간의 데이터 통신용 회로.4. Important uses of the invention: circuits for data communication between processors.

Description

프로세서간의 통신을 위한 데이터 송수신회로Data transmission / reception circuit for communication between processors

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 프로세서간의 데이터 통신회로도, 제4도는 제3도의동작을 설명하기 위한 타이밍도, 제5도는 본 발명에 따른 제3도의 회로를 이용한 프로세서간 통신 회로도.3 is a data communication circuit diagram between the processors according to the present invention, FIG. 4 is a timing diagram for explaining the operation of FIG. 3, and FIG. 5 is an inter processor communication circuit diagram using the circuit of FIG. 3 according to the present invention.

Claims (4)

어드레스 신호와 데이터 입출력단자와, 제1기록제어신호단자및 제1출력제어신호단자를 가지는 메모리를 구비한 데이터 통신회로에 있어서, 외부로부터 입력되는 기록 어드레스 신호와 독출 어드레스 신호증 하나의 어드레스 신호를 송신신호제어신호의 논리에 따라 선택하여 상기 메모리의 어드레스단자로 공급하는 어드레스 선택수단과, 제2기록제어신호의 입력에 응답하여 사이즈 데이터를 래치하여 출력하는 사이즈 데이터 저장수단과, 외부로부터의 제2기록제어신호에응답하여 송신제어신호를 상기 어드레스 선택수단으로 공급하며 독출완료신호의 입력에 응답하여 상기 송신제어신호를 차단하는 송신제어신호 발생수단과, 상기 독출완료신호에 응답하여 송신준비신호를 출력함과 동시에 상기 송신제어신호를차단하고 상기 제2기록제어신호에 응답하여 상기 송신 준비신호를 차단하는 송신준비신호 발생수단으로 구성함을 특징으로 하는 데이터 통신회로.A data communication circuit having an address signal, a data input / output terminal, a memory having a first write control signal terminal and a first output control signal terminal, comprising: a write address signal input from an external source and a read address signal signal; Address selection means for selecting according to the logic of the transmission signal control signal and supplying it to the address terminal of the memory, size data storage means for latching and outputting the size data in response to the input of the second write control signal, and from the outside. A transmission control signal generating means for supplying a transmission control signal to said address selection means in response to a write control signal, and blocking said transmission control signal in response to an input of a read completion signal, and a transmission ready signal in response to said read completion signal; Outputs a signal and simultaneously blocks the transmission control signal and The data communications circuit, characterized in that the means consists of a transmission ready signal is generated in response by blocking the transmission ready signal. 제1항에 있어서, 외부로부터 입력되는 독출제어신호에 응답하여 상기 사이즈 데이터 저장수단의 출력단자로부터 출력되는 사이즈 데이터를 게이팅하여 출력하는 사이즈 데이터 출력수단을 더 포함함을 특징으로하는 데이터 통신회로.The data communication circuit according to claim 1, further comprising size data output means for gating and outputting size data output from an output terminal of the size data storage means in response to a read control signal input from the outside. . 어드레스단자와 데이터 입력단자 및 데이터 출력단자, 제1기록제어신호 단자 및 제1출력제어신호단자를 가지는 메모리를 구비하여 제1프로세서와 제2프로세서간의 데이터 통신을 위한 데이터 통신회로에 있어서, 상기 제1프로세서 및 제2프로세서로부터 각각 출력되는 기록 어드레스 신호와 독출 어드레스 신호 중 하나의 어드레스 신호를 송신신호제어 신호의 논리에 따라 선택하여 상기 메모리의 어드레스단자로 공급하는 멀티플렉서와, 상기 제1프로세서로부터의 제2기록제어신호의 입력에 응답하여 입력되는 사이즈 데이터를 래치하여 출력하는 사이즈 레지스터와, 상기 제2기록제어신호에응답하여 송신제어신호를 상기 제2프로세서로 출력함과 동시에 상기 멀티플렉서의 제어단자로 공급하며 리세트 신호의 입력에 응답하여 상기 송신제어신호를 차단하는 제1제어신호 발생수단과, 상기 제2프로세서로부터의 독출완료신호에 응답하여 송신준비신호를 상기 제1프로세서로 출력하고 상기 제2기록제어신호에 응답하여 상기 송신준비신호의 출력을 차단하는제2제어신호 발생수단과, 파워온 리세트 및 상기 독출완료신호의 입력에 응답하여 상기 제1제어신호 발생수단을 리세트하는 리세트수단과, 상기 사이즈 레지스터로부터의 출력을 제2프로세서로부터의 제2독출제어신호의 입력에 응답하여 상기제2프로세서로 게이팅 출력하는 사이즈 데이터 전송수단으로 구성함을 특징으로하는 데이터 통신회로.A data communication circuit for data communication between a first processor and a second processor, comprising a memory having an address terminal, a data input terminal, a data output terminal, a first write control signal terminal, and a first output control signal terminal. A multiplexer for selecting one of the write address signal and the read address signal output from the first processor and the second processor according to the logic of the transmission signal control signal, and supplying the address signal to the address terminal of the memory; A size register for latching and outputting size data input in response to the input of the second write control signal, and outputting a transmit control signal to the second processor in response to the second write control signal and at the same time as the control terminal of the multiplexer. The transmission control signal in response to an input of a reset signal A first control signal generating means for blocking and outputting a transmission ready signal to the first processor in response to a read completion signal from the second processor, and blocking the output of the transmission ready signal in response to the second write control signal. Second control signal generating means, reset means for resetting the first control signal generating means in response to the input of the power-on reset and the read completion signal, and an output from the size register from the second processor. And size data transfer means for gating and outputting to the second processor in response to an input of the second read control signal. 제2항에 있어서, 상기 사이즈 데이터 전송수단은, 상기 사이즈 레지스터의 각각의 출력단자에 일측의 단자가 접속되며 타측의 단자로 입력되는 제2독출제어신호의 입력에 응답하여 상기 일측단자의 데이터를 게이팅하여 상기 제2프로세서로 전송하는 앤드게이트 어레임을 특징으로하는 데이터 통신회로.The terminal of claim 2, wherein the size data transmission means has one terminal connected to each output terminal of the size register and in response to an input of a second read control signal input to the other terminal. And an AND gate array for gating and transmitting the gate signal to the second processor. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940038102A 1994-12-28 1994-12-28 Data transceiving circuit for inter communication processor KR0185600B1 (en)

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KR1019940038102A KR0185600B1 (en) 1994-12-28 1994-12-28 Data transceiving circuit for inter communication processor

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KR960025033A true KR960025033A (en) 1996-07-20
KR0185600B1 KR0185600B1 (en) 1999-05-15

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