KR960020514A - Multipoint Control Unit Structure for Video Conference - Google Patents

Multipoint Control Unit Structure for Video Conference Download PDF

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Publication number
KR960020514A
KR960020514A KR1019940029975A KR19940029975A KR960020514A KR 960020514 A KR960020514 A KR 960020514A KR 1019940029975 A KR1019940029975 A KR 1019940029975A KR 19940029975 A KR19940029975 A KR 19940029975A KR 960020514 A KR960020514 A KR 960020514A
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KR
South Korea
Prior art keywords
decoder
fifo1
video
fifo8
mcu
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KR1019940029975A
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Korean (ko)
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KR0141319B1 (en
Inventor
김성민
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김준성
사단법인 고등기술원연구원 연구조합
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Priority to KR1019940029975A priority Critical patent/KR0141319B1/en
Publication of KR960020514A publication Critical patent/KR960020514A/en
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Publication of KR0141319B1 publication Critical patent/KR0141319B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/14—Systems for two-way working
    • H04N7/15—Conference systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/434—Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
    • H04N21/4341—Demultiplexing of audio and video streams
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/25—Pc structure of the system
    • G05B2219/25431—Dual Port memory
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/26—Pc applications
    • G05B2219/2615—Audio, video, tv, consumer electronics device

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Telephonic Communication Services (AREA)

Abstract

본 발명은 랜 카드(10), 부호/복호기(30) 및 PC인터페이스(40)에 연결되어 있는 PC(2-1∼2-n)내의 화상 회의 시스템의 MCU(20)구조에 관한 것으로서, 비트 스트림 형태로 MCU내에 입력된 오디오 및 영상 데이타의 ID를 디코딩하여 디코딩 신호를 출력하는 어드레스 디코더(23)와; 각각의 ID에 해당하는 데이타 버퍼에 매인트라프레임(Intraframe)당 번지가 갱신되는 적어도 두개 이상의 디코더 선입 선출 버퍼(FIFO1-FIFO8)며, 어드레스 디코더의 디코딩신호에 따라 입력된 오디오 및 비데오 데이타를 상기 디코더 선입 선출버퍼(FIFO1-FIFO8)에 선택적으로 인가하는 A/V분리기(22)와; 상기 디코더 선입선출 버퍼(FIFO1-FIFPO8)에 연결되며, 상기 선입 선출 버퍼(FIFO1-FIFO8)의 영상 및 오디오 신호를 선택적으로 출력하는 디코더 입력 스위치(24)와; 상기 PC인터페이스 회로(40)와 연결되며, PC(2-1∼2-n)에서 전달되는 모든 정보를 전달 및 전송받는 듀얼 포트 램(Dual Port RAM)(25)과; MCU(20)로 인가되는 부호화된 비데오 및 오디오 데이타에 헤더를 삽입시키는 헤더 발생기(26)와; 헤더발생기(26)에 연결되며 헤더 발생기(26)로부터 인가되는 압축된 데이타의 전송시의 비트 전송 비를 맞추어 출력하는 엔코더 선입 선출 버퍼(FIFO)와; 상기 MCU(20)의 각 구성 부분을 제어하는 마이크로 프로세서(27)을 구비한다.The present invention relates to the structure of the MCU 20 of the video conferencing system in the PCs 2-1 to 2-n connected to the LAN card 10, the code / decoder 30 and the PC interface 40. An address decoder 23 for decoding an ID of audio and video data input into the MCU in a stream form and outputting a decoded signal; At least two decoder first-in, first-out buffers (FIFO1-FIFO8) whose address is updated per intraframe in a data buffer corresponding to each ID. An A / V separator 22 selectively applying to the first-in, first-out buffers FIFO1-FIFO8; A decoder input switch (24) connected to the decoder first-in first-out buffer (FIFO1-FIFPO8) and selectively outputting video and audio signals of the first-in first-out buffer (FIFO1-FIFO8); A dual port RAM 25 connected to the PC interface circuit 40 and receiving and transmitting all the information transmitted from the PCs 2-1 to 2-n; A header generator 26 for inserting a header into the encoded video and audio data applied to the MCU 20; An encoder first-in first-out buffer (FIFO) connected to the header generator 26 and outputting in accordance with a bit transfer ratio at the time of transmission of the compressed data applied from the header generator 26; It is provided with a microprocessor 27 for controlling each component of the MCU (20).

따라서, 본 발명은 화상 회의에 참석한 참석자의 모습을 복수로 선택하여 시청한 수 있게 하므로서, 화상 회의를 원활하게 진행할 수 있다는 효과가 있다.Accordingly, the present invention enables the video conference to be performed smoothly by allowing the user to select and view a plurality of attendees who attend the video conference.

Description

화상 회의용 멀티 포인트 콘트롤 유니트 구조Multipoint Control Unit Structure for Video Conference

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명을 수행하는데 필요한 전체 랜 망의 개념도,2 is a conceptual diagram of an entire LAN network required to carry out the present invention;

제3도는 본 발명에 따른 멀티 포인트 콘트롤 유니트를 구비하는 퍼스널콤퓨터의 내부 블럭도,3 is an internal block diagram of a personal computer having a multi-point control unit according to the present invention;

제4도는 본 발명에 따른 멀티 포인트 콘트롤 유니트의 구조를 도시한 블럭도.4 is a block diagram showing the structure of a multi-point control unit according to the present invention.

Claims (1)

비트 스트립 형태로 멀티 포인트 콘트롤 유니트내에 입력된 오디오 및 영상 데이타의 ID를 더코딩하여 디코딩 신호를 출력하는 어드레스 디코더(23)와; 각각의 ID에 해당하는 데이타 버퍼에 매 인트라프레임(Intraframe) 당 번지가 갱신되는 적어도 두개 이상의 디코더 선입 선출버퍼(FIFO1-FIFO8)와; 어드레스 디코더의 디코딩 신호에 따라 입력된 오디오 및 비데오 데이타를 상기 디코더 선입 선출 버퍼(FIFO1-FIFO8)에 선택적으로 인가하는 A/V분리기(22)와; 상기 디코더 선입 선출 버퍼(FIFO1-FIFO8)에 연결되며, 상기 디코더 선입 선출 버퍼(FIFO1-FIFO8)의 영상 및 오디오 신호를 선택적으로 출력하는 디코더 입력 스위치(24)와; 상기 PC인터페이스 회로(40)와 연결되며, PC(2-1∼2-n)에서 전달되는 모든 정보를 전달 및 전송받는 듀얼 포트 램(Dual Port RAM) (25)과; MCU(20)로 인가되는 부호화된 비데오 및 오디오 데이타에 헤더를 삽입시키는 헤더 발생기(26)와; 헤더 발생기(26)에 연결되며 헤더 발생기(26)로 부터 인가되는 압축된 데이타의 전송시의 비트 전송 비를 맞추어 출력하는 엔코더 선입 선출버퍼(FIFO9)와; 상기 MCU(20)의 각 구성 부분을 제어하는 마이크로 프로세서(27)를 구비하는 화상 회의 시스템의 멀티 포인트 콘트롤 유니트구조.An address decoder 23 for decoding an ID of audio and video data input into the multi-point control unit in the form of a bit strip and outputting a decoded signal; At least two decoder first-in first-out buffers FIFO1-FIFO8 whose addresses are updated for each intraframe in a data buffer corresponding to each ID; An A / V separator (22) for selectively applying audio and video data input according to a decoding signal of an address decoder to the decoder first-in first-out buffers (FIFO1-FIFO8); A decoder input switch (24) connected to the decoder first-in first-out buffer (FIFO1-FIFO8) and selectively outputting video and audio signals of the decoder first-in first-out buffer (FIFO1-FIFO8); A dual port RAM 25 connected to the PC interface circuit 40 and receiving and transmitting all information transmitted from the PCs 2-1 to 2-n; A header generator 26 for inserting a header into the encoded video and audio data applied to the MCU 20; An encoder first-in, first-out buffer (FIFO9) connected to the header generator 26 and outputting in accordance with a bit transfer ratio at the time of transmission of the compressed data applied from the header generator 26; A multi-point control unit structure of a video conferencing system having a microprocessor (27) for controlling each component of the MCU (20). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940029975A 1994-11-16 1994-11-16 Multi-point control unit architecture for video conference KR0141319B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940029975A KR0141319B1 (en) 1994-11-16 1994-11-16 Multi-point control unit architecture for video conference

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Application Number Priority Date Filing Date Title
KR1019940029975A KR0141319B1 (en) 1994-11-16 1994-11-16 Multi-point control unit architecture for video conference

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KR960020514A true KR960020514A (en) 1996-06-17
KR0141319B1 KR0141319B1 (en) 1998-06-15

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