KR960019986A - Power Supply Noise Reduction Circuit of Analog / Digital Converter - Google Patents

Power Supply Noise Reduction Circuit of Analog / Digital Converter Download PDF

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Publication number
KR960019986A
KR960019986A KR1019940031295A KR19940031295A KR960019986A KR 960019986 A KR960019986 A KR 960019986A KR 1019940031295 A KR1019940031295 A KR 1019940031295A KR 19940031295 A KR19940031295 A KR 19940031295A KR 960019986 A KR960019986 A KR 960019986A
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KR
South Korea
Prior art keywords
analog
digital converter
zero point
signal
output
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KR1019940031295A
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Korean (ko)
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KR0129475B1 (en
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손보형
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배순훈
대우전자 주식회사
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Priority to KR1019940031295A priority Critical patent/KR0129475B1/en
Publication of KR960019986A publication Critical patent/KR960019986A/en
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Publication of KR0129475B1 publication Critical patent/KR0129475B1/en

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Abstract

본 발명은 아날로그/디지탈 변환기에 관한 것으로서, 더욱상세하게는 교류전원이 포함되어 입력되는 아날로그 입력전압을 디지탈 변환할때 교류전원의 제로점에서 아날로그/디지탈 변환하여 교류전원의 영향을 받지 않은 입력전압의 디지탈값을 구할 수 있도록 한 아날로그/디지탈 변환기의 전원 노이즈 제거회로에 관한 것으로, 교류 입력전압으로부터 제로점을 검출하는 제로점 검출부(90)와, 상기 제로점 검출부(90)의 출력과 콘트롤러(30)의 SC신호를 근거로 디지탈 변환을 지연하기 위한 지연시간을 발생하는 RS플립/플롭(60)과, 상기 RS플립/플롭(60)의 출력으로 SC신호를 발생하여 아날로그/디지탈 변환기(20)에 공급하는 단안정 멀티바이브레이트(50)와, 상기 RS플립/플롭(60)의 출력과 아날로그/디지탈 변환기(20)의 EOC신호를 논리곱하여 콘트롤러(30)에 EOC신호로 공급하는 앤드 게이트(40)로 구성된다.The present invention relates to an analog / digital converter, and more particularly, an input voltage not affected by an AC power source by analog / digital conversion at a zero point of the AC power source when digitally converting an analog input voltage including an AC power source. The present invention relates to a power supply noise canceling circuit of an analog / digital converter capable of obtaining a digital value of the present invention, wherein the zero point detection unit (90) detects a zero point from an AC input voltage, and the output and controller of the zero point detection unit (90). RS flip / flop 60 for generating a delay time for delaying the digital conversion based on the SC signal of 30), and an SC / A signal is generated by outputting the RS flip / flop 60 to the analog-to-digital converter 20. ) And the EOC signal of the controller 30 by multiplying the monostable multi-vibration 50 and the output of the RS flip / flop 60 and the EOC signal of the analog-to-digital converter 20. It consists of the end gate 40 which supplies a signal.

Description

아날로그/디지탈 변환기의 전원 노이즈 제거회로Power Supply Noise Reduction Circuit of Analog / Digital Converter

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 따른 아날로그 입력전압을 디지탈 전압으로 변환하기 위한 개략블록도.3 is a schematic block diagram for converting an analog input voltage into a digital voltage according to the present invention.

Claims (4)

아날로그 입력전압값을 디지탈 값으로 변환하는 아날로그/디지탈 변환(20)와, 상기 아날로그/디지탈 변환기(20)의 출력값을 근거로 입력값을 측정하거나 후단의 동작을 제어하는 콘트롤러(30)를 구비하는 아날로그/디지탈 변환기에 있어서, 교류 입력전압으로부터 제로점을 검출하는 제로점 검출부(90)와, 상기 제로점 검출부(90)의 출력과 콘트롤러(30)의 SC신호를 근거로 디지탈 변환을 지연하기 위한 지연시간을 발생하는 RS플립/플롭(60)과, 상기 RS플립/플롭(60)의 출력으로 SC신호를 발생하여 아날로그/디지탈 변환기(20)에 공급하는 단안정 멀티바이브레이트(50)와, 상기 RS플립/플롭(60)의 출력과 아날로그/디지탈 변환기(20)의 EOC신호를 논리곱하여 콘트롤러(30)에 EOC신호로 공급하는 앤드 게이트(40)를 포함하여 구성되어짐을 특징으로 하는 아날로그/디지탈 변환기의 전원 노이즈 제거회로.An analog / digital conversion 20 for converting an analog input voltage value into a digital value, and a controller 30 for measuring an input value or controlling a subsequent operation based on the output value of the analog / digital converter 20. In the analog / digital converter, a zero point detection unit (90) for detecting a zero point from an AC input voltage, a delay for digital conversion based on the output of the zero point detection unit (90) and the SC signal of the controller (30). RS flip / flop 60 for generating a delay time, and monostable multivibration 50 for generating an SC signal to the output of the RS flip / flop 60 and supplying it to the analog / digital converter 20; And an AND gate 40 which logically multiplies the output of the RS flip / flop 60 and the EOC signal of the analog / digital converter 20 and supplies it to the controller 30 as an EOC signal. Digital Power source noise elimination circuit of ventilation. 제1항에 있어서, 아날로그/디지탈 변환기(20)의 전단에는 입력전압을 샘플링 및 일정시간 동안 홀딩시키는 샘플링 및 홀딩부(10)가 구성되어짐을 특징으로 하는 아날로그/디지탈 변환기의 전원 노이즈 제거회로.The power supply noise canceling circuit of claim 1, wherein the front end of the analog / digital converter (20) comprises a sampling and holding unit (10) configured to sample and hold the input voltage for a predetermined time. 제1항에 있어어서, RS플립/플롭(60)의 R단자에는 콘트롤러(30)의 SC신호가 인가되고 S단자에는 제로점 검출부(90)의 출력이 인가되어짐을 특징으로 하는 아날로그/디지탈 변환기의 전원 노이즈 제거회로.The analog-to-digital converter according to claim 1, wherein the SC signal of the controller 30 is applied to the R terminal of the RS flip / flop 60, and the output of the zero point detection unit 90 is applied to the S terminal. Power supply noise canceling circuit. 제1항에 있어서, 제로점 검출부(90)는 트랜스(T) 및 저항(R)을 매개로 입력된 교류전원와 접지점의 레벨을 비교하는 비교기(70)와, 상기 비교기(70)출력을 일정폭의 방형파로 변환하는 단안정멀티바이브레이트(80)으로 구성되어짐을 특징으로 하는 아날로그/디지탈 변환기의 전원 노이즈 제거회로.The zero point detector 90 is a comparator 70 for comparing the level of the AC power and the ground point inputted through the transformer (T) and the resistor (R) and the output of the comparator 70 by a predetermined width. The noise reduction circuit of the analog-to-digital converter characterized by consisting of a monostable multivibration (80) for converting into a square wave. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940031295A 1994-11-25 1994-11-25 Noise-removing circuit of anglog/digital converter KR0129475B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940031295A KR0129475B1 (en) 1994-11-25 1994-11-25 Noise-removing circuit of anglog/digital converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940031295A KR0129475B1 (en) 1994-11-25 1994-11-25 Noise-removing circuit of anglog/digital converter

Publications (2)

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KR960019986A true KR960019986A (en) 1996-06-17
KR0129475B1 KR0129475B1 (en) 1998-10-01

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KR1019940031295A KR0129475B1 (en) 1994-11-25 1994-11-25 Noise-removing circuit of anglog/digital converter

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KR0129475B1 (en) 1998-10-01

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