KR960019276A - V Seed Envelope Error Mode Detection Circuit - Google Patents
V Seed Envelope Error Mode Detection Circuit Download PDFInfo
- Publication number
- KR960019276A KR960019276A KR1019940030861A KR19940030861A KR960019276A KR 960019276 A KR960019276 A KR 960019276A KR 1019940030861 A KR1019940030861 A KR 1019940030861A KR 19940030861 A KR19940030861 A KR 19940030861A KR 960019276 A KR960019276 A KR 960019276A
- Authority
- KR
- South Korea
- Prior art keywords
- output
- envelope
- circuit
- level
- signal
- Prior art date
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- Digital Magnetic Recording (AREA)
Abstract
본 발명은 헤드에서 검출된 엔벨로프 신호에 이상이 있을 경우 이를 검출하여 사용자에게 알려줌으로써 불량한 재생화면이 나오는 것을 사전에 방지할 수 있도록 한 브이 씨 알의 엔벨로프 이상 모드 검출회로에 관한 것으로 재생 헤드(1)로부터 검출된 신호를 일정레벨로 증폭시키는 헤드 앰프(2)와, 상기 헤드 앰프의 출력에서 엔벨로프에 포함된 고주파 성분을 제거하는 로우 패스 필터(3)와, 상기 로우 패스 필터의 출력 신호를 직류 성분으로 변환시키는 정류 회로(4)와, 상기 정류 회로의 출력값의 피크치를 일정하게 유지시키는 피크 홀드 회로(5)와, 상기 피크 홀드 회로의 출력 전압과 기준 전압을 비교하여 해당 레벨의 신호를 출력시키는 비교수단(6)과, 상기 비교수단의 출력 레벨에 따라 스위칭되어 엔벨로프 검출 상태를 표시해 주는 표시수단(7)을 포함하여 이루어진다.The present invention relates to an V-envelope abnormal mode detection circuit which detects an error in an envelope signal detected by a head and informs a user so that a bad playback screen can be prevented. A head amplifier (2) for amplifying the signal detected by a predetermined level, a low pass filter (3) for removing high frequency components included in an envelope from the output of the head amplifier, and an output signal of the low pass filter. A rectifier circuit 4 for converting the component into a component, a peak hold circuit 5 for maintaining a constant peak value of the output value of the rectifier circuit, and an output signal of the corresponding level is output by comparing the output voltage and the reference voltage of the peak hold circuit. Comparison means 6 and display means 7 which switch according to the output level of the comparison means to display the envelope detection state. It comprise.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제1도는 본 발명에 따른 엔벨로프 이상 모드 회로도이다.1 is an envelope abnormal mode circuit diagram according to the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940030861A KR960019276A (en) | 1994-11-23 | 1994-11-23 | V Seed Envelope Error Mode Detection Circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940030861A KR960019276A (en) | 1994-11-23 | 1994-11-23 | V Seed Envelope Error Mode Detection Circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
KR960019276A true KR960019276A (en) | 1996-06-17 |
Family
ID=66648782
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940030861A KR960019276A (en) | 1994-11-23 | 1994-11-23 | V Seed Envelope Error Mode Detection Circuit |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR960019276A (en) |
-
1994
- 1994-11-23 KR KR1019940030861A patent/KR960019276A/en not_active Application Discontinuation
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
WITN | Withdrawal due to no request for examination |