KR960016230A

KR960016230A - Demultiplexer for MPEG2 Streams

Info

Publication number: KR960016230A
Application number: KR1019940028266A
Authority: KR
Inventors: 박용준
Original assignee: 배순훈; 대우전자 주식회사
Priority date: 1994-10-31
Filing date: 1994-10-31
Publication date: 1996-05-22
Also published as: KR0159564B1

Abstract

본 발명은 멀티플렉싱된 MPEG2의 전송스트림을 디멀티플렉싱 하는 하드웨어적 구조를 단순화시킨 디멀티플렉서에 관한 것으로, PID값이 0인 TS패킷스트림들을 입력받아, TS패킷의 헤더를 제거하고 데이터에 해당하는 부분만을 PID메모리로 전송하는 PAT디패키타이저; PID값을 가진 TS패킷스트립중에서 PMT TS패킷스트림을 입력받아 PMT 테이블의 데이터를 PID 메모리로 전송하는 PMT디패키타이저; PAT디패키타이저와 PMT디패키타이저를 제어하여, 기록인에이블신호를 전송하는 PID제어기; PAT 테이블데이터를 억세서 할때는 사용자에 의해 설정된 프로그램넘버를 어드레스로 사용하고, PMT 테이블데이터를 억세서할때는 PID값을 어드레스로 사용하는 PID메모리; PID 제어기에서 출력하는 기록인에이블 신호에 따라 데이터를 기록하는 디멀티 로직부; 디멀티 로직부의 기본스트림을 디코딩하는 기본스트림디코더를 포함하도록 구성한다.The present invention relates to a demultiplexer that simplifies the hardware structure for demultiplexing a multiplexed MPEG2 transport stream. The present invention relates to a demultiplexer that receives a TS packet stream having a PID value of 0, removes a header of a TS packet, and then PIDs only a portion corresponding to data. PAT depacketizer for transmitting to the memory; A PMT depacketizer which receives a PMT TS packet stream from a TS packet strip having a PID value and transmits data of a PMT table to a PID memory; A PID controller for controlling a PAT depacketizer and a PMT depacketizer to transmit a write enable signal; A PID memory that uses a program number set by a user as an address when accessing PAT table data and a PID value as an address when accessing PMT table data; A demultiplex logic unit for recording data according to a write enable signal output from the PID controller; And a base stream decoder for decoding the base stream of the demultiplex logic unit.

Description

Demultiplexer for MPEG2 Streams

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 엠팩2스트림을 위한 디멀티플렉서장치도,2 is a demultiplexer device for an MPEG-2 stream according to the present invention;

제3도는 제2도를 설명하기 위한 타이밍 다이어그램도,3 is a timing diagram for explaining FIG.

제4도는 본 발명에 대한 디멀티플렉서장치도,4 is a demultiplexer device according to the present invention;

제5도는 제4도의 디멀티플렉서에서 구현된 상세회로도.5 is a detailed circuit diagram implemented in the demultiplexer of FIG.

Claims

A demultiplexer for MPEG3 streams having a PAT depacketizer, a PMT depacketizer, a PID controller, and the like; A PAT depacketizer which receives TS packet streams having a PID value of 0, removes a header of the TS packet, and transmits data of the PAT table to the PID memory only in a portion corresponding to the data; A PMT depacketizer which receives a PMT TS packet stream from a TS packet strip having a PID value indicating a PMT table and transmits data of the PMT table to a PID memory; A PID controller for controlling the PAT depacketizer and the PMT depacketizer to transmit a write enable signal; Store the data of the PAT table and the PMT table output from the PAT depacketizer and the PMT depacketizer, and when accessing the PAT table data, use the program number set by the user and the PMT table data PID memory that uses PID value as address; A demultiplex logic unit which records the data according to a write enable signal output from the PID controller; The demultiplexer for MPEG2 stream, characterized in that it comprises a decoder for the base stream of the demultiplex logic unit.

※ Note: The disclosure is based on the initial application.