KR960016148A - Phase-locked loop circuit - Google Patents

Phase-locked loop circuit Download PDF

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Publication number
KR960016148A
KR960016148A KR1019940028230A KR19940028230A KR960016148A KR 960016148 A KR960016148 A KR 960016148A KR 1019940028230 A KR1019940028230 A KR 1019940028230A KR 19940028230 A KR19940028230 A KR 19940028230A KR 960016148 A KR960016148 A KR 960016148A
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KR
South Korea
Prior art keywords
signal
input
receiving
outputting
response
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KR1019940028230A
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Korean (ko)
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KR100346725B1 (en
Inventor
박선규
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김광호
삼성전자 주식회사
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Priority to KR1019940028230A priority Critical patent/KR100346725B1/en
Publication of KR960016148A publication Critical patent/KR960016148A/en
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Publication of KR100346725B1 publication Critical patent/KR100346725B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/187—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop
    • H03L7/189—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop comprising a D/A converter for generating a coarse tuning voltage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

1. 본 발명은 위상 동기 루우프 회로에 관한 것으로서, 특히 위상동기를 이루기 위한 외부 입력신호의 중단시에도 최종 위상 동기를 유지하는 위상동기 루우프 회로에 관한 것이다.1. The present invention relates to a phase locked loop circuit, and more particularly, to a phase locked loop circuit which maintains a final phase lock even when an external input signal for phase synchronization is interrupted.

2. 본 발명은 위상동기를 이루기 위한 외부 입력신호의 중단시에 위상동기가 이루어지지 않는 단점을 해결하기 위한 위상 동기 루우프 회로를 향한 것이다.2. The present invention is directed to a phase locked loop circuit for solving the disadvantage that phase synchronization is not achieved when an external input signal for phase synchronization is interrupted.

3. 본 발명은 위상동기를 이루기 위한 외부 입력신호의 중단시에 최종 위상 동기상태를 홀딩하고 상기 홀딩된 위상동기상태에 대응하는 출력신호를 생성출력한다.3. The present invention holds the final phase synchronization state when the external input signal for phase synchronization is stopped and generates and outputs an output signal corresponding to the held phase synchronization state.

4. 본 발명은 디지탈 통신시스템에서 특히 중요하게 사용될 수 있다.4. The present invention can be used particularly important in digital communication systems.

Description

위상 동기 루우프 회로Phase-locked loop circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 바람직한 일 실시예에 따른 위상 동기 루우프 회로의 블럭 구성도.2 is a block diagram of a phase locked loop circuit according to an exemplary embodiment of the present invention.

Claims (4)

위상 동기 루우프 회로에 있어서; 외부 입력신호와 소정 내부클럭을 입력받으며, 상기 두 입력신호의 위상을 비교하여 그 위상차를 위상신호로 출력하며, 상기 입력신호의 입력유무에 대응하는 입력감지신호를 출력하는 위상비교수단과; 상기 위상차신호를 입력받아 레벨변환하여 출력하는 레벨변환수단과; 상기 입력감지 신호에 대응하여 소정 동기유지신호를 생성하며, 상기 레벨변환된 위상차신호를 입력받아 상기 동기유기신호와 비교하고, 그 비교결과에 대응하여 상기 동기유지신호를 증감하는 동기유지수단과; 상기 동기유지신호와 상기 레벨변환된 위상차신호를 각각 입력받으며, 상기 입력감지신호에 대응하여 상기 두 입력신호중 선택된 하나의 입력신호를 출력하는 스위칭수단과; 상기 스위칭수단의 출력신호를 입력받아 이에 대응하는 소정 발진 신호를 생성출력하는 발진수단과; 상기 발진신호를 입력받아 소정 분주비로 분주하여 상기 위상비교기의 상기 내부클럭으로 출력하는 분주수단으로 구성함을 특징으로 하는 위상 동기 루우프 회로.A phase locked loop circuit; A phase comparison means for receiving an external input signal and a predetermined internal clock, comparing the phases of the two input signals, outputting a phase difference as a phase signal, and outputting an input detection signal corresponding to the presence or absence of the input signal; Level converting means for receiving the phase difference signal and level converting the resultant signal; Synchronizing holding means for generating a predetermined synchronizing holding signal in response to the input sensing signal, receiving the level-converted phase difference signal, comparing with the synchronizing organic signal, and increasing or decreasing the synchronizing holding signal in response to the comparison result; Switching means for receiving the synchronization holding signal and the level-converted phase difference signal, respectively, and outputting one input signal selected from the two input signals in response to the input sensing signal; Oscillating means for receiving an output signal of the switching means and generating and outputting a predetermined oscillating signal corresponding thereto; And a divider means for receiving the oscillation signal and dividing the oscillation signal at a predetermined division ratio to output the internal clock of the phase comparator. 제1항에 있어서, 상기 동기유지수단이; 입력중임을 알리는 상기 입력감지신호에 대응하여 소정 동기유지 신호를 생성하며, 소정 제어신호를 입력받아 이에 대응하여 상기 동기유지신호를 증감하여 출력하는 동기유지 신호생성수단과, 상기 동기유지신호와 상기 레벨변환된 위상차신호를 입력받아 상기 두 입력신호의 전압레벨을 비교하고 그 비교결과에 대응하는 상기 제어신호를 출력하는 전압레벨 비교수단으로 구성함을 특징으로 하는 위상 동기 루우프 회로.2. The apparatus as claimed in claim 1, wherein the synchronization maintaining means; Synchronizing sustain signal generating means for generating a predetermined synchronizing sustain signal in response to the input sensing signal indicating that an input is being input, receiving a predetermined control signal and increasing and decreasing the synchronizing sustain signal in response thereto; And a voltage level comparison means for receiving a level-converted phase difference signal, comparing the voltage levels of the two input signals, and outputting the control signal corresponding to the comparison result. 제2항에 있어서, 상기 동기유지신호생성수단이, 입력중임을 알리는 상기 입력감지신호에 대응하여 카운터 인에이블되며, 상기 제어신호를 입력받아 이에 대응하여 업/다운 카운팅제어되어 그 카운팅값을 출력하는 업/다운 카운팅수단과, 상기 카운팅값을 입력받아 아나로그상태의 동기유지신호로 변환출력하는 아나로그 변환수단으로 구성함을 특징으로 하는 위상 동기 루우프 회로.The method according to claim 2, wherein the synchronization sustain signal generating means is counter enabled in response to the input sensing signal informing that the input is in progress, and receives the control signal and up / down counting control corresponding thereto to output the counting value. And an analog conversion means for receiving the counting value and converting and outputting the counting signal into a synchronous sustain signal in an analog state. 제1항 또는 제2항 또는 제3항에 있어서, 상기 스위칭수단이; 상기 동기유지신호와 상기 레벨변환된 위상차신호를 각각 입력받으며, 상기 입력신호가 입력중임을 알리는 상기 입력감지신호에 응답하여 상기 레벨변환된 위상차신호를 출력하고, 상기 입력신호가 입력중단되었음을 알리는 상기 입력감지신호에 응답하여 상기 동기유지신호를 출력하는 스위칭수단임을 특징으로 하는 위상 동기 루우프 회로.The method of claim 1, wherein the switching means; Receiving the synchronization sustain signal and the level shifted phase difference signal, respectively, outputting the level shifted phase difference signal in response to the input detection signal indicating that the input signal is being input, and indicating that the input signal has been stopped. And a switching means for outputting the synchronization holding signal in response to an input sensing signal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940028230A 1994-10-31 1994-10-31 Phase locked loop circuit KR100346725B1 (en)

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Application Number Priority Date Filing Date Title
KR1019940028230A KR100346725B1 (en) 1994-10-31 1994-10-31 Phase locked loop circuit

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Application Number Priority Date Filing Date Title
KR1019940028230A KR100346725B1 (en) 1994-10-31 1994-10-31 Phase locked loop circuit

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KR960016148A true KR960016148A (en) 1996-05-22
KR100346725B1 KR100346725B1 (en) 2002-10-25

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