KR960015606B1 - Processor state management method using backward and forward navigation method - Google Patents

Abstract

(41,42) investigating the processor state in forward and reverse direction; (43-46) writing the abnormal processor information in the abnormal state information message when the processor state is abnormal, and otherwise, transmitting the state test completion signal; and (47,48) repeating the step of writing the forward/reverse state message in an OMP state information table after repeating until the last state test processor, and ending.

Description

Processor State Management Method Using Forward and Reverse Navigation Techniques

1 is a message reference state test example for explaining the present invention.

2 is a processor configuration diagram of each module of the ATM switch to which the present invention is applied.

3 is a plan view of ATM switch processors to which the present invention is applied.

4 is a process flow diagram for a processor state management method according to the present invention.

The present invention relates to a processor state management method using forward and reverse navigation techniques.

Operational Maintenance Processor (OMP) in a distributed processing system such as an electronic exchanger, in addition to the processor's state management function, is related to the operation and maintenance of the system. It takes a lot of load because it needs to handle the collection management function, subscriber management function, etc. Thus, periodically testing the state of all processors in the electronic exchange adds more load to the OMP. However, periodic processor state management is essential for accurate state identification of the electronic exchange system and rapid recovery of abnormal processors. However, in the existing state management method, the OMP requires a state test to each processor each time, and the processor that is requested for the state test should send a response to the OMP every time whether the state is normal or abnormal. Therefore, the existing method causes a bottleneck that overloads the OMP because every processor sends and receives an OMP message each time. Due to such an overload, the conventional method was unable to perform frequent processor state tests, which made it difficult to determine the exact state of the processor and quickly recover the abnormal processor.

In order to solve the problems of the prior art, the present invention performs a dual state management test using a processor address table and two processor status messages, thereby periodically and accurately correcting the processor status without overloading the OMP. The purpose of the present invention is to provide a processor state management method using forward and reverse navigation techniques.

In order to achieve the above object, the present invention provides a processor state management method applied to an ATM switch, wherein the state of the processor is checked in the forward and reverse directions by operating a timer while the previous processor sends a state test request message to the current processor. First step to do; After performing the first step, if the processor state is abnormal, the abnormal processor information is recorded in the abnormal state information message. If the processor state is normal, the status test completion message is transmitted, the previous processor stops the timer, and then the current processor and the next processor. Second step of changing; And performing a third step of repeating the final state test processor after performing the second step, and then repeating and ending the process of comparing the forward and reverse state information messages to the OMP state information table.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a diagram illustrating a message reference state test for explaining the present invention, (a) shows a case in which the processor under state test is normal, and (b) shows a case in which the processor under state test is abnormal.

FIG. 2 is a diagram showing the processor configuration of each module of the ATM switch to which the present invention is applied. FIG.

As shown in the figure, an ATM switch is composed of one CIM (Central Interconnection Moudle) and n ASM (Access Switching Module). The processors that make up CIM include OMP (1), NSCP (2), MMCP (3), BCP (4), CIMP (5), RCIP (6), GSP (7), NTP (8), etc. The constituent processors include SCP (9), TCP (10), BCP (11), ASMP (12), NTP (13), and SH (14).

OMP (1) (Operation and Maintenance Processor) has an auxiliary storage device such as magnetic tape (MT) and disk (Disk) to oversee a series of operations and maintenance related functions in the system. Charge records, statistics, maintenance, and management information are stored in the MT, and generic programs and data are stored on disk.

NSCP (2) (Network Synchronization Control Processor) controls the network synchronizer device.

MMCP (3) (Man MaChine Control Processor) is used to hard copy the output data and VDU (Visual Display Units) including the system console to enable communication between the operator and the system or between the operation center and the system. Control input and output devices such as printers.

BCP (4) (11) (Broadcasting Call Processor) is a processor that manages call / access control for providing multiple access (broadcasting) related service and is located in CIM and ASM respectively. Control multiple access functions.

The CIMP (5) (Central Interconnection Maintenance Processor) manages the control of maintenance tasks in the CIM, such as fault collection and testing of hardware resources in the CIM, and reports each status to the higher processor, OMP.

The Remote Center Interface Processor (RCIP) 6 controls communication with a remote operation center or a Telecommunication Management Network (TMN), and performs a protocol conversion function as necessary.

The Global Service Processor (GSP) 7 controls service devices provided throughout the system, such as recording announcements.

NTP (8) (11) (Number Translation Processor) responds to the number translation request from each SCP, TCP, and BCP, and performs ASM number translation and link identifier (ID) translation contained in each ASM.

Subscriber Call Processor (SCP) is a processor that performs call processing of general subscribers using the User Network Interface (UN) protocol, and with subscriber matching circuits, lock control, user parameter control (UPC), priority control, Perform overall traffic control such as weight control (congestion control).

TCP (10) (Trunk Call Processor) is a processor that performs call processing with a network using NNI (Network Node Interface) protocol and calls / connection control for incoming / outgoing calls with a trunk line matching circuit. It performs all functions necessary for registration with the network.

The Access Switching Maintenance Processor (ASMP) (12) is responsible for controlling the maintenance tasks within the ASM, including fault collection and testing at the hardware level.

Signaling Handler (SH) 14 terminates the signal information cell on the UNI / NNI protocol and processes the signal information with SCP (9), TCP (10) or BCP (4) (11).

In the proposed method, one processor representing each ASM is responsible for the state management of the processors in the module, and the OMP 9 in the CIM is in charge of the state management of the entire exchange. The status management of each ASM is dedicated to SCP, and the status management of CIM is dedicated to CIMP (5).

SCP (9) of ASM1 is represented as SCP1 and SCP of ASMn is represented as SCPn.

OMP (1) sends a status test request message to CIMP (5) to check the status of CIM, activates the first timer, and sends a status test request message to SCPn to check the status of ASMn, and activates a second timer. The CIMP (5) and SCPn which received the status test request message send the status test completion message to OMP (1) if the processors in the module are normal and send the status test request message to the representative processors (SCP1 and SCPn-1) of the next module. Start the timer.

OMP (1) receiving the status test completion message from CIMP (5) and SCPn stops the two timers and sends abnormal processor status information message to CIMP (5) and SCPn respectively and when this message returns through the whole exchange system. To perform other functions.

If the CIMP (5) that receives the abnormal processor status information message does not receive a status test completion message from SCP1 until the timer expires, the status of SCP1 is regarded as abnormal and the SCPMP is added to the abnormal processor status information message and the status test request message is returned. Send SCP2 and start the timer.

When SCPn receives an abnormal processor status information message and receives a status test completion message from SCPn-1, it stops the timer and sends the abnormal processor status information message to SCPn-1. SCPn-1 sends a status test request message to SCPn-2 and starts a timer.

If the above processes are carried out in the ascending and descending order of each SCP 9, the OMP 1 finally receives two abnormal processor status information messages. The OMP 1 collects two messages to determine an abnormal processor and records them in a status information table. Processors recorded abnormally in both abnormal processor status information messages gathered in OMP (1) are certainly considered abnormal, and processors recorded abnormally in only one abnormal processor status information message are unclear. Send a request message. If there is no status test completion message until the timer expires, it is defined as an abnormal processor. Repeat the above procedure.

4 is a process flow diagram according to the present invention.

First, the basic principle of the present invention will be described.

When each processor is initialized, the Operation and Maintenance Processor (OMP) has a state information table having attributes of all processors' names, addresses, and states.

Each processor has a processor address table that contains configuration information about what processors exist before and after it.

During the state test, an abnormal processor status information message containing the addresses of the abnormal processors is roamed (41).

State management begins with the OMP sending a state test request message in the reverse order of the processor address and starting the timer (42).

A processor that has requested a status test tests its status and, if the result is normal, sends a status test completion message to the processor requesting the status test (45), and then sends a status test request message to the processor (before or after the processor). The timer is activated while sending (46).

When the processor requesting the status test receives the status test completion message from the processor which has been requested for the status test before the timer expires, the processor sends an abnormal processor status information message that it has been sleeping to the processor that has been requested for the status test (44).

If the processor requesting the status test does not receive the status test completion message until the timer expires, the processor determines that the status of the tested processor is abnormal and adds the address of the processor to the abnormal processor status information message that it has. Sends a status test request message to the next processor of the requested processor and starts the timer (47).

In this way, when an abnormal processor status message is returned to OMP starting from OMP and in the reverse order of processor address and reverse, OMP collects these two messages to determine an abnormal processor and records them in the status information table (48).

Repeat the above process.

Accordingly, the present invention as described above, by using the timer and two abnormal processor status messages to distribute the load for the processor state management to each processor in the OMP (1), while removing the excessive OMP load and at the same time periodic state test This allows for fast and accurate state management of the processors.

Claims (1)

CLAIMS 1. A processor state management method applied to an ATM switch, comprising: a first step (41, 42) of checking a state of a processor in a forward and reverse manner by operating a timer while a previous processor sends a state test request message to a current processor; After performing the first steps 41 and 42, if the processor state is abnormal, the abnormal processor information is recorded in the abnormal state information message. If the processor state is normal, the processor sends a state test completion message and the previous processor stops the timer and then Second steps 43 to 46 for changing the processor and the next processor; After performing the second steps (43 to 46), repeating to the last state test processor and then forward; And a third step (47, 48) of repeating the process of comparing the reverse state information message and recording the OMP state information table in the OMP state information table.