KR960015592A

KR960015592A - Nonvolatile Semiconductor Memory Device

Info

Publication number: KR960015592A
Application number: KR1019950039515A
Authority: KR
Inventors: 쇼지 고야마; 도시카쓰 진보
Original assignee: 가네꼬 히사시; 닛폰 덴키 가부시키가이샤
Priority date: 1994-10-31
Filing date: 1995-10-31
Publication date: 1996-05-22
Also published as: JP2647027B2; JPH08129893A

Abstract

비 휘발성 반도체 메모리 장치는 메모리 셀이 편차없이 소거되고 소거 시간이 줄여지는데 제공된다. 데이터 래치 회로는 워드 라인의 소정수의 모든 장치에 제공된다. 워드 라인 장치의 셀의 비 소거 또는 소거를 지시하는 상태정보는 데이터 래치 회로에 기억된다. 이 소거 동작은 상기 정보에 기초하여 이미 소거된 워드 라인에 접속된 셀이 스킵된다.Nonvolatile semiconductor memory devices are provided in which memory cells are erased without variation and the erase time is reduced. The data latch circuit is provided to all devices of a predetermined number of word lines. Status information indicating non-erasing or erasing of the cells of the word line device is stored in the data latch circuit. This erase operation skips the cells connected to word lines that have already been erased based on the information.

이 방법으로, 클럭간의 소거 편차는 억압된다. 상기 셀 입증 동작은 소거 시간의 감소에 기인하여 셀의 위치에 데이터 래치의 상태 정보를 판독함으로서 소거와 입증 동작으로 생략된다.In this way, the erase deviation between clocks is suppressed. The cell verify operation is omitted in the erase and verify operation by reading the state information of the data latch at the cell position due to the reduction of the erase time.

Description

Nonvolatile Semiconductor Memory Devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 제1실시예에 따른 비휘발성 반도체 메모리 장치를 도시하는 블럭도,1 is a block diagram showing a nonvolatile semiconductor memory device according to a first embodiment of the present invention;

제3도는 제1도의 실시예의 소거 동작을 실명하는 흐름도.3 is a flow chart for blinding the erase operation of the embodiment of FIG.

Claims

A memory cell array in which memory transistors each having a control gate such as a memory cell and a floating gate are arranged in a matrix manner in a column and a row direction; A word line connected to said control gate of said memory transistor in each furnace; A bit line connected to the drain of the memory transistor of each column; A source line grouped by a plurality of columns and connected to the sources of the memory transistors in each group; An X decoder for selecting a word line according to the address signal; A Y decoder for selecting a bit line according to the address signal; Stores information on a cell indicating whether all cells connected to the word line are erased, and if all cells are erased when erasing a cell connected to another word line, the word line is set to an erase suppression level. A data latch circuit provided on each word line for selecting; An erase end detection circuit for detecting whether the word line is selected to erase all the memory transistors connected to the word line from the cell state information and the output of the X decoder; And skip control means for selecting a word line connected to the memory transistor to be erased and skipping the erase operation of the word line in the erase mode when detected by the erase end detection circuit for erasing all the memory transistors connected to the word line. A nonvolatile semiconductor memory device.

12. The erase of the word line as claimed in claim 1, wherein the skip control means skips the erase and verify operation of all cells in an erase mode when the erase end detection circuit detects erasing all memory transistors connected to the word line. And controlling the attestation operation.

3. A nonvolatile semiconductor memory device according to claim 1 or 2, wherein each of said data circuits stores cell state information in memory transistors connected to at least two word lines.

4. The erasing termination detection circuit according to any one of claims 1 to 3, wherein the erasing termination detection circuit is composed of two transistors connected in series to each word line, and the gate of each transistor corresponds to the word line. And a cell state information of a data latch circuit and an output of an X decoder for the word line.

A memory cell array in which memory transistors each having a control gate such as a memory cell and a floating gate are arranged in a matrix manner in a column and a row direction; A word line connected to said control gate of said memory transistor in each furnace; A bit line connected to a drain of the memory transistor of each column; a source line connected to a source of the memory transistor; An X decoder for selecting a word line according to the address signal; A Y decoder for selecting a bit line according to the address signal; Stores information on a cell indicating whether all cells connected to the word line are erased, and when all cells are erased when erasing a cell connected to another word line, the word line is set to an erase suppression level. A data latch circuit provided to each word line by setting; An erase end detection circuit for detecting whether the word line is selected as a state for erasing all the memory transistors connected to the word line from the cell state information and the output of the X decoder; And skip control means for selecting a word line connected to the memory transistor to be erased and skipping the erase operation of the word line in the erase mode when detected by the erase end detection circuit for erasing all the memory transistors connected to the word line. A nonvolatile semiconductor memory device.

※ Note: The disclosure is based on the initial application.