KR960011969B1 - Internal cell format in the atm switch - Google Patents

Abstract

an idle cell bit(IDL:IDleCELL) having one bit indicating a presence of an idle state of an inputted cell; a multi-connecting display bit(MTC:MulTicasting Cell) having one bit in order to discriminate a multi-connection call; a sending-collecting stage routing information area(Org-ASW-RI) having six bits; a cell delay priority bit(CDP:Cell Delay Priority) having one bit indicating a priority according to a delay; a routing information area(CSW_RI) of a distributed stage having seven bits; a cell shape bit(CET: CELL Type) having two bits set according to a kind of a received control entity of a control information message; a routing information area(Term_ASW_Ri) of a receiving-collecting stage having six bits.

Description

Internal Cell Format Structure of Asynchronous Transfer Mode Exchange System

1 is a schematic diagram of a general ATM switching system,

2 is a structural diagram of an internal cell format according to the present invention;

3 is a configuration diagram of a CET bit according to the present invention;

4 is an exemplary internal message communication path between control entities.

The present invention relates to an internal cell format structure in an Asynchronous Transfer Mode (ATM) switching system, which is a subject that provides a path configuration for user information transmission in a broadband integrated telecommunication network (B-ISDN).

The ITU-TS adopts the Asynchronous Transfer Mode (ATM) method, which divides all information into cells of a certain size as a basic method of transmission for realizing a broadband integrated information communication network. The cell basic format is recommended at the point of registration (UNI) and the point of registration with the relay line (NNI).

However, the ATM switching system has a self-routing switch to switch the high-speed cell to be input. For the self-routing of the input cell, routing information indicating the physical address of the switch network is provided in the input cell header of the ITU-TS recommended basic format. Should be added. In addition, various control information for control in the system is added to the cell header.

Therefore, the basic cell format recommended by lTU-TS should be converted into the internal cell format suitable for system configuration inside the system. However, in Korea, there are no technologies for configuring an exchange system and consequently the internal cell format.

Accordingly, the present invention uses the asynchronous transfer mode method recommended by the ITU-TS to provide high-speed switching, efficient cell processing, various multi-access services, and high-quality data service. Its purpose is to provide a cell format structure.

In order to achieve the above object, the present invention provides a data format structure of an asynchronous delivery mode communication system recommended by ITU-TS having a 5-head cell header area and a 48-octet user information area. 1-bit idle cell bit (IDL: IDLecel1) indicating presence or absence, 1-bit multiple access indication bit (MTC: MulTicasting Cell) to distinguish multiple access codes, and 6-bit originating group routing information area (Org_ASW_RI) 1 set of cell delay priority bits (CDP: Cell Delay Priority) indicating priority of delay, routing information area (CSW_RI) of 7-bit distribution stage, and destination control entity of control and information messages. And a 2 bit cell type bit (CET: CEll Type) and a 6 bit bit routing information area (Term_ASW_RI).

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic diagram of a distributed asynchronous transfer mode switching system in which user information is switched on a cell basis, and is composed of k collection terminals and 1 distribution terminal, which is recommended by the ITU-TS for registration with users. It supports NNI (Network Node Interface) matching protocol for matching with UNI (User Network Interface) matching protocol.

In addition, the converging stage has N NN and other magnetic routing switches to provide N 155.520Mbps bidirectional ports, among which n port is used as the user side and m port is used as the distribution side. = n + m) to perform the function of the concentrator having the condensation ratio. Therefore, the tangent ratio of the collecting end can be used in the range of 1: 1 to maximum (N-1): 1. The distribution stage is a purely interconnector with no call processing that exchanges information between concentrators and is a thoroughly passive switch network.

Therefore, the distribution end is a self-routing switch based on routing information in the cell header, and the bandwidth of the internal link between the aggregation end and the distribution end is managed by the aggregation end. In addition, the path selection of the information transmission is determined by the originating converging group and the terminating concentrating group, and the virtual channel identifier (VCI) of the cell is not converted in the distribution terminal. In addition, since the distribution stage is a passive switch network, the switching path in the distribution stage is a single path. Operation and Maintenance Processor (OMP) located in the distribution stage is connected to one port of the distribution stage to restart the system, operation control function, test, various traffic information, statistics related to system operation, maintenance and management. And subscriber management functions such as manual management of billing information, subscriber registration, cancellation, and attribute change, and system resource management functions.

FIG. 2 is a block diagram of an internal cell format proposed for high-speed self-routing, efficient cell processing, and various multi-access services in an asynchronous delivery mode switching system such as the first diagram.

The system shown in FIG. 1 is configured in three stages (calling collection end-distributing end-calling end) and needs routing information, which is a physical address of each switch network, for cell self-routing at each end.

Therefore, the internal cell format is 6 bits in the routing information area (first octet, bit 6-bit 1) of the generation aggregation end, 7 bits in the routing information area (second octet, bit 7-bit 1) of the distribution end, and called destination. Six bits are allocated to the routing information area (third octet, bit 6-bit 1) at the leading end. The aggregation switch network can be up to 64 × 64 (2 ⁶ = 64) and the distribution switch network can be up to 128 × 128 (2 ⁷ ).

Among the basic cell formats, the ITU-TS recommended cell header is 5 octets. The 5th octet of the 5 octets is the HEC (Header Error Conto1) area in which the CRC value of the header is embedded, and the rest are GFC (General Flow Control), VPI / VCI, Payload Type (PT) and Cell Loss Priority (CLP).

However, the ITU-TS recommendation indicates that when the value of the first to fourth octets is '00 00 000lH ', the user information area is meaningless idle cell, which is terminated at the physical layer. Therefore, the first bit (first octet, bit 8) of the internal cell header added to the idle cell (IDL: IDLe cel1) bit is also set by the input header conversion table. Indicates an idle cell.

In broadband broadband telecommunication network, it is necessary to provide various services. Especially, it is essential to provide services for multiple access such as broadcasting. Therefore, when setting up a call, it distinguishes the call for multiple access and sets the second bit (first octet, bit 7) of additional cell header when changing all cells inputted from the same connection from input head conversion table to internal cell format. To indicate that it is a multi-access set (MTC: MulTicasting Cel1). The VPI / VCI region of the cell displaying the multi-access cell is input as an MCN (Multicasting Channel Number) from the input head conversion table during internal cell conversion.

Although the CLP bit is allocated for loss priority control in the ITU-TS recommended basic cell header, the quality of service (QoS) of the service not only causes cell loss but also cell delay. Therefore, the delay sensitive (CDP: Ce1l Delay Priority) bit is controlled in the 1st bit (bit 8) of the 2nd octet besides the cell header by distinguishing the delay sensitive and insensitive calls according to the type of service required for call setup. Set it. The switch network performs loss and delay priority control using the CLP bit of the basic cell header and the CDP bit included in the inner cell header.

Communication between all control entities in the system is through its own switch network, so control and information messages between control entities are cell-by-cell. The control entities of the system are largely divided into processors and controllers embedded in hardware, and CET (CEl1 Type) bits are set together with the third degree according to the type of the destination control entity of the control and information messages.

If the cell is a user information cell, the CET bits are set to '00'. Otherwise, the cell is a cell for control and information messages used in the system. First, if CET is '11', it indicates that the cell destination of the control entity is a processor connected to a link switched by routing information regardless of the destination. If CET is '01', it means that the cell destination is a convergent terminal, and in particular, the cell is received by the controller connected to the route to which the cell is routed. If the CET is '10', it means that the cell destination is a distribution terminal, and in particular, that the cell is received by the controller connected to the route to which the cell is routed.

Figure 4 shows the internal message cell transfer penalty between control entities using CET.

As in the first diagram, the system is largely composed of a collection and distribution stage.

The aggregation end is an ASNM (Access Switching Network Module), which is a switch for self-routing an input cell according to routing information located in an internal cell header, an ASWC (Access Switching Controller), which is a controller of the ASNM, and a SIM that performs a bonding function with a subscriber. (Subscriber Interface Module), which is a controller that controls it, has a Subscriber Interface Module Controller (SIMC), and consists of SCP (Subsciber Contro1 Processor), a processor that controls all of its call processing processes.

The distribution stage includes an Interconnection Switching Network Module (ISNM), which is a switch network for interconnecting the aggregation ends, and a Central Switching Controller (CSWC), a controller that controls them.OMP (Operation) is a processor that performs maintenance functions throughout the system. and Maintenance Processor).

The address for internal message cell transfer between control entities consists of routing information and CET for the links of the switch network to which the control entity is physically connected. Some examples of path and address configuration for internal message transmission between control entities in the system configuration as shown in FIG. 4 are as follows.

Case 1) The address of the SCP of the collection group to transmit the internal message delivery cell to the OMP of the distribution group: Calling group routing information (Org_ASW_RI) + distribution routing information (CSW_RI) + '11' (CET bit)

Case 2) The SCP of the collecting party sends an internal message to the CSWC of the distribution group.

Address for cell transmission: Routing group routing information (Org_ASW_Rl) Distribution terminal routing information (CSW_RI) + '01' (CET bit)

Case 3) A fleet of SCPs sends internal messages to their SIMCs

Address for cell transmission: Routing information of originating group (Org_ASW_RI) + '01' (CET bit)

Case 4) The CSWC of the distribution team sends an internal message to the SCP of the collection team.

Address for cell information: distribution end routing information (CSW_RI) + destination end routing information (Term_ASW_RI) + 'l1' (CET bit)

Accordingly, the present invention as described above enables fast cell self-routing in the asynchronous delivery mode system recommended by the ITU-TS. In addition, the idle cells can be efficiently separated in the high-speed cell flow, and since the cells for multiple accesses are distinguished, various multi-access services can be provided together with the MCN. In addition to the cell loss recommended by the ITU-TS, priority control on delays that greatly affect the quality of service (QoS) of the user is possible, thereby providing high quality service to the user. In addition, the characteristics of the present invention is to classify the internal message cells of the system again according to the type of destination so that communication between the processors in the system and between the processor and the controller can be made in the cell unit through its own switch network without a separate communication means It was. This reduces the amount of hardware in the system by not using a separate means for communication between internal control entities, and improves reliability of control information transmission by using a high speed / high reliability ATM switch network as a communication means for control entities. You can.

Claims (3)

In the data format structure of the asynchronous delivery mode communication system recommended by ITU-TS having a 5-octet cell header area and a 48-octet user information area, a 1-bit idle cell bit indicating whether or not an input cell is idle ( IDL: IDLeCELL), 1-bit multiple access indication bit (MTC: MulTicasting Cell) to distinguish multiple access codes, 6-bit originating group routing information area (Org_ASW_RI), 1-bit indicating priority for delay Cell Delay Priority Bit (CDP: Cell De1ay Priority), 7-bit Distribution Stage Routing Information Area (CSW_RI), and 2-bit Cell Type Bit (CET: CEll Type) set according to the type of the destination control entity of the control information message. ) And the 6-bit terminating group's routine information area (Term_ASW_ri), further comprising an internal cell format structure of an asynchronous delivery mode switching system. The cell type bit (CET) of claim 1, wherein the cell type bit (CET) indicates that the cell represents a user information cell in a set state of '00', and is a cell for control and information messages used inside the system in another set state. An internal cell format structure of an asynchronous delivery mode switching system. The processor of claim 2, wherein the set state of the cell type bit (CET) excluding '00' is '11', wherein a processor connected to a link of which a destination of a cell of a control entity is switched by routing information regardless of a destination. '01' indicates that the cell's destination is the controller in the aggregation end connected to the link to which the cell is routed, and '10' indicates that the cell's destination is the controller in the distribution end connected to the link to which the cell is routed. An internal cell format structure of an asynchronous delivery mode switching system.