KR960011701A - Memory with error handling - Google Patents

Memory with error handling Download PDF

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Publication number
KR960011701A
KR960011701A KR1019940024346A KR19940024346A KR960011701A KR 960011701 A KR960011701 A KR 960011701A KR 1019940024346 A KR1019940024346 A KR 1019940024346A KR 19940024346 A KR19940024346 A KR 19940024346A KR 960011701 A KR960011701 A KR 960011701A
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KR
South Korea
Prior art keywords
error
data
network
error handling
detection
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KR1019940024346A
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Korean (ko)
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KR960016399B1 (en
Inventor
한우종
오귀현
박경
윤석한
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양승택
재단법인 한국전자통신연구소
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Priority to KR1019940024346A priority Critical patent/KR960016399B1/en
Publication of KR960011701A publication Critical patent/KR960011701A/en
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0736Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766Error or fault reporting or storing
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2215Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Debugging And Monitoring (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

본 발명은 프로세서, 연결망, 기억장치로 구성되는 시스템에 오류검출 또는 검출 및 교정기능을 지원하는 경우에 있어서 기억장치의 오류검출 또는 교정동작과 연결망의 동작을 최대한 중첩시킬 수 있도록 하는 기억장치에 관한 것으로, 기억장치로 부터 읽혀진 데이타가 오류가 없다는 것이 확인되기 이전에 출력 인터페이스를 동작시키고 연결망의 동작을 시작시켜 데이타를 프로세서로 전송하기 직전 까지 진행하도록 한다.The present invention relates to a memory device capable of superimposing the error detection or correction operation of the storage device and the operation of the network as much as possible in the case of supporting an error detection or detection and correction function in a system consisting of a processor, a network, and a storage device. Before the data read from the memory can be confirmed that there is no error, operate the output interface, start the connection network, and proceed just before sending the data to the processor.

이로써, 읽기에 기억장치 접근 시간이 길어지는 부작용을 없애고 오류 취급 기능이 부가되지 않은 것과 유사하게 기억장치 접근시간을 최소화하여 시스템의 성능을 향상시켜 준다.This eliminates the side-effect of longer memory access times for reading and minimizes memory access time, similarly to the lack of error handling.

Description

오류취급 기능을 갖는 기억장치Memory with error handling

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 다중프로세서 시스템의 개략도.2 is a schematic diagram of a multiprocessor system.

Claims (3)

각각 적어도 하나 이상씩의 프로세서(1,4a~4n)와 기억장치(3,6a~6m)가 연결망(2,5)을 통하여 연결되고, 상기 프로세서(1,4a~4n)는 상기 연결망(2,5)를 통하여 상기 기억장치(3,6a~6m)를 액세스하는 시스템에 있어서; 상기 기억장치(3,6a~6m) 각각은 상기 연결망(2,5)의 동작을 계속 관찰하여 그 요구를 받아들이고 또한 복수개의 기억장치(6a…6m)가 사용될 경우에는 그 요구가 자신에 대한 요구인 지를 판별하는 기능도 유지하여 상기 연결망(2,5)에 나타난 상기 프로세서(1,4a…4n)의 요구가 항상 응답될 수 있는 조건을 유지하는 입력 인터페이스 수단(8)과; 상기 입력 인터페이스(8)으로 부터의 프로세서 요구를 받아들여 상기 기억장치(3,6a…6m)의 고유의 내부기능을 제어하기 위해 쓰기동작의 경우 오류검출 및 교정부호의 생성을 제어하고, 읽기의 경우 읽어 낸 데이타와 상기 오류검출 및 교정부호를 이용하여 오류의 검출 및 교정이 이루어 지도록 제어하고, 그리고 교정시에 교정된 데이타 및 부호 정보를 저장하는 내부동작 제어수단(9)과; 상기 내부동작 제어수단(9)에 의해 제어되어, 상기 쓰기동작의 경우 입력된 데이타를 위한 오류검출용 부호를 생성하여 저장 및 유지하고, 읽기의 경우 읽힌 데이타와 부호를 입력으로 하여 데이타의 오류검출 또는 검출 및 교정을 하여 출력하는 오류 취급수단(10)과; 상기 내부동작 제어수단(9) 및 상기 오류 취급수단(10)의 출력신호에 따라 상기 연결망(2,5)을 통하여 요구한 상기 프로세서(1,4a…4n)로 데이타를 전송하기 위한 동작을 수행하는 출력 인터페이스 수단(11)을 포함하는 것을 특징으로 하는 오류취급기능을 갖는 기억장치.At least one or more processors 1, 4a to 4n and storage devices 3, 6a to 6m are connected through the network 2 and 5, respectively, and the processors 1, 4a to 4n are connected to the network 2 A system for accessing said storage devices (3,6a-6m) through (5); Each of the storage devices 3, 6a to 6m continuously observes the operation of the network 2 and 5 to accept the request, and when a plurality of storage devices 6a to 6m are used, the request is a request for itself. Input interface means (8) for maintaining a function of discriminating recognition and maintaining conditions under which a request of the processors (1,4a ... 4n) shown in the connection network (2,5) can always be answered; In order to accept the processor request from the input interface 8 and to control the internal functions unique to the storage devices 3, 6a ... 6m, in the case of the write operation, the error detection and the generation of the correction code are controlled, Internal operation control means (9) for controlling the detection and correction of the error by using the read data and the error detection and correction code, and for storing the corrected data and code information at the time of correction; Controlled by the internal operation control means 9, in the case of the write operation, the error detection code for the input data is generated, stored and maintained, and in the case of reading, the error data of the data is detected by inputting the read data and the code. Or error handling means (10) for detecting and correcting the output; According to the output signals of the internal operation control means 9 and the error handling means 10, an operation for transmitting data to the processor 1, 4a ... 4n requested through the connection network 2, 5 is performed. And an output interface means (11). 제1항에 있어서, 상기 오류 취급수단(10)은 상기 기억장치로 부터 읽혀진 데이타가 오류가 없다는 것이 확인되기 이전에 상기 출력 인터페이스 수단(11)을 동작시키고 상기 연결망의 동작을 시작시켜 데이타를 상기 프로세서로 전송하기 직전까지 진행하도록 하는 것을 특징으로 하는 오류취급기능을 갖는 기억장치.The data processing apparatus according to claim 1, wherein the error handling means (10) operates the output interface means (11) and starts the operation of the connection network before the data read from the storage device is confirmed that there is no error. Memory with error handling, characterized in that the progress until just before sending to the processor. 제1항에 있어서, 상기 기억장치는 상기 출력 인터페이스수단과 상기 내부동작 제어수단 및, 상기 오류 취급수단 사이에 버퍼수단을 부가적으로 포함하고; 상기 오류취급수단은 상기 기억장치로 부터 읽혀진 데이타가 오류가 없다는 것이 확인되기 이전에 연결망의 동작을 시작시켜 데이타를 상기 프로세서로 보내는 연결망의 제반준비동작과 데이타의 오류검출 또는 검출 및 교정시간을 중첩시키는 것을 특징으로 하는 오류취급기능을 갖는 기억장치.2. The apparatus according to claim 1, wherein said storage device further comprises buffer means between said output interface means, said internal operation control means, and said error handling means; The error handling means superimposes all the preparation operations of the network to send data to the processor before starting the operation of the network before confirming that the data read from the memory is error-free, and overlapping the error detection or detection and correction time of the data. And a memory device having an error handling function. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940024346A 1994-09-27 1994-09-27 Memory device with error handling function KR960016399B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7989136B2 (en) 2007-04-02 2011-08-02 Samsung Electronics Co., Ltd. Photoresist composition and method of forming a photoresist pattern using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7989136B2 (en) 2007-04-02 2011-08-02 Samsung Electronics Co., Ltd. Photoresist composition and method of forming a photoresist pattern using the same

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