KR960010933B1

KR960010933B1 - Manufacturing method of semiconductor laser diode

Info

Publication number: KR960010933B1
Application number: KR1019920016734A
Authority: KR
Inventors: 안형수; 임진혁; 시상기
Original assignee: 엘지전자 주식회사; 구자홍
Priority date: 1992-09-15
Filing date: 1992-09-15
Publication date: 1996-08-13
Also published as: KR940008174A

Abstract

sequentially forming a double hetero structure layer (2), a quantum well layer (3), and the first Si penetration preventive layer (4) on the first conductivity type substrate (1); depositing an insulating layer (6) on the first Si penetration preventive layer (4) and selectively etching it to a predetermined width; removing both insulating layers (6) and the first Si penetration preventive layer (4); and sequentially forming the third clad layer (9) and a cap layer (10) on the entire surface.

Description

Manufacturing method of semiconductor laser diode

제1도는 종래으 반도체 레이저 다이오드의 구조를 나타낸 단면도.1 is a cross-sectional view showing the structure of a conventional semiconductor laser diode.

제2도는 본 발명의 제1실시예의 공정단면도.2 is a process cross-sectional view of the first embodiment of the present invention.

제3도는 본 발명의 제2실시예의 공정단면도.3 is a process cross-sectional view of a second embodiment of the present invention.

제4도는 본 발명의 제3실시예의 공정단면도.4 is a process cross-sectional view of a third embodiment of the present invention.

제5도는 본 발명의 제4실시예의 공정단면도.5 is a process cross-sectional view of a fourth embodiment of the present invention.

제6도는 본 발명의 제5실시예의 공정단면도.6 is a process cross-sectional view of a fifth embodiment of the present invention.

제7도는 본 발명의 제6실시예의 공정단면도.7 is a process cross-sectional view of a sixth embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 기판 2 : 더블헤테로 구조층1: Substrate 2: Double hetero structure layer

3 : 양자 우물층 4 : 제1 Si침투방지막3: quantum well layer 4: first Si penetration prevention film

5 : 제2Si침투방지막 6 : 절연막5: 2nd Si penetration prevention film 6: Insulation film

7 : 포토레지스트 8 : 전류제한층7: photoresist 8: current limiting layer

9 : 제3클래드층 10 : 캡층9: 3rd clad layer 10: cap layer

본 발명은 반도체 레이저 다이오드에 관한 것으로, 특히 선택적 성장에 의해 내부 전류주입홈을 형성할 때 발생되는 표면 결합을 제거하기에 적당하도록 한 반도체 레이저다이오드의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor laser diodes and, more particularly, to a method of manufacturing a semiconductor laser diode adapted to remove surface bonds generated when forming internal current injection grooves by selective growth.

일반적으로 레이저 다이오드는 안정된 단일 모드와 낮은 문턱 전류에서의 구동 및 높은 양자효율을 갖기위해 굴절율 도파로 형태의 구조를 갖고 있다. 이러한 굴절율 도파로 형태의 레이저 다이오드 구조는 내부에 전류를 제한시켜 주기 위한 내부 전류차단층을 갖고 있으며, 기판의 형태에 따라 전류차단층이 활성층의 위쪽 혹은 아래쪽에 위치하여 전류를 효과적으로 제한하게 되는데 이와같은 형태의 레이저 다이오드는 전류제한층을 성장시킨후 에칭에 의해 전류주입구를 형성하였다.In general, the laser diode has a refractive waveguide structure in order to have stable single mode, low threshold current driving, and high quantum efficiency. The refractive waveguide type laser diode structure has an internal current blocking layer for limiting the current therein, and the current blocking layer is located above or below the active layer to effectively limit the current, depending on the shape of the substrate. The laser diode of the type formed a current inlet by etching after growing the current limiting layer.

제1도는 종래 에칭에 의해 전류주입홈이 형성된 반도체 레이저 다이오드의 구조를 단면으로 나타낸 것으로 먼저 제조공정을 살펴보면 기판(11)위에 제1클래드층(12), 활성층(13), 제2클래드층(14), 제1반도체층(15), 전류제한층(16), 제2반도체층(17)을 차례로 형성하고 상기 제2반도체층(17)을 다시 H2 O2 : NH4OH=5 : 1의 에칭용액으로 선택적 제거한후 HF 용액으로 전류제한층(16)의 소정부분을 경사지게 에칭하고 제3클래드(18)과 캡층(19)을 형성한 후 상기 캡층(19) 상면과 기판(11) 하면에 각각 전극(20)(20a)를 형성하였다.FIG. 1 is a cross-sectional view showing a structure of a semiconductor laser diode in which current injection grooves are formed by conventional etching. First, a manufacturing process will be described. The first cladding layer 12, the active layer 13, and the second cladding layer 11 may be formed on a substrate 11. 14), the first semiconductor layer 15, the current limiting layer 16, and the second semiconductor layer 17 are formed in this order, and the second semiconductor layer 17 is again etched with H 2 O 2: NH 4 OH = 5: 1. After selective removal, the predetermined portion of the current limiting layer 16 is inclinedly etched with HF solution, and the third cladding 18 and the capping layer 19 are formed, and then electrodes are formed on the upper surface of the capping layer 19 and the lower surface of the substrate 11, respectively. (20) (20a) was formed.

이러한 반도체 레이저 다이오드에 있어서 만일 전류제한층(16)과 제1반도체층(15)이 같은 성질의 반도체 일 경우 선택적 에칭이 불가능하기 때문에 초기 제1반도체층(15)이 없이 바로 제2클래드층(14)이 노출된 형태로 제조되었다.In such a semiconductor laser diode, if the current limiting layer 16 and the first semiconductor layer 15 are semiconductors of the same property, selective etching is impossible, and thus the second cladding layer immediately without the initial first semiconductor layer 15 ( 14) was prepared in exposed form.

따라서, 전류제한층(16)의 GaAs와 제1클래드층(12)의 AlGaAs를 선택적 용액으로 에칭하여 전류제한층(16)의 전류주입홈을 제거하면 노출된 홈부위의 제1클래드층(12)이 AlGaAs층이므로 산화가 일어나게 되어 레이저 다이오드 특성에 크게 영향을 주기 때문에 종래에는 이러한 산화를 방지하기 위해 전류제한층(16)으로 Al0.7Ga0.3As를 이용하였다.Therefore, when GaAs of the current limiting layer 16 and AlGaAs of the first cladding layer 12 are etched with a selective solution to remove the current injection grooves of the current limiting layer 16, the first cladding layer 12 of the exposed groove portion is removed. Since Al) is an AlGaAs layer, oxidation occurs and greatly affects laser diode characteristics. Thus, Al0.7Ga0.3As is used as the current limiting layer 16 to prevent such oxidation.

또한, 상기와 같은 종래의 레이저 다이오드는 전극(20)(20a)을 통하여 전류, 즉 캐리어가 주입되면 전류 제한층(16)의 효과적인 전류 제한으로 낮은문턱전류를 얻을 수 있었다.In addition, in the conventional laser diode as described above, when a current, that is, a carrier is injected through the electrodes 20 and 20a, a low threshold current can be obtained due to the effective current limit of the current limiting layer 16.

그러나, 종래 에칭에 의한 전류주입홈 형성은 대량생산을 위한 대면적인 웨이퍼에서 그 단일성(Uniformity)을 유지하기가 어렵고 에칭을 2회에 걸쳐 실시해야 되는 번거로움이 있으며 경사지게 에칭할 때 에칭율은 조정하기가 어려울 뿐만 아니라 에칭후의 전류주입홈의 측면 산화가 발생하는 문제가 있다.However, current injection groove formation by conventional etching is difficult to maintain its uniformity on large wafers for mass production, and it is cumbersome to perform two etchings, and the etching rate is adjusted when the etching is inclined. Not only is it difficult to do so, but there is also a problem in that lateral oxidation of the current injection groove after etching occurs.

또한, 선택적 에칭을 하기 위하여 전류제한층(16)으로 Al0.8GaAs를 사용하기 때문에 산화를 방지하기 위한 제2반도체층(17)를 필연적으로 형성시켜야 하는 문제가 있다.In addition, since Al 0.8 GaAs is used as the current limiting layer 16 for selective etching, there is a problem in that a second semiconductor layer 17 is necessarily formed to prevent oxidation.

본 발명은 이와같은 종래의 문제점을 해결하기 위한 것으로 전류주입홈을 선택적으로 에칭하여 형성하지 않고 선택적으로 성장시켜 형성하는 반도체 레이저 다이오드의 제조방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method of manufacturing a semiconductor laser diode which is formed by selectively growing the current injection grooves instead of selectively etching them.

이와같은 목적을 달성하기 위한 본 발명은 같은 성질의 결정체에서 같은 물질의 결정체를 형성할 수 있는 원리를 이용하여 홈을 용이하게 선택적으로 성장시킬 수 있음을 특징으로 한다.The present invention for achieving the above object is characterized in that the groove can be easily and selectively grown using the principle of forming crystals of the same material in the crystals of the same property.

이하에서 본 발명의 실시예를 첨부된 도면에 의하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

제2도는 본 발명의 제1실시예로 (A)와 같이 기관(n-GaAs) (1)위에 MOCVD법으로 두께가 0.5μm 이상인 버퍼층(n-GaAs)/제1클래드층(n-Al0.45GaAs)/활성층(언도프드 Al0.14 aAs)/두께가 0.2-0.65μm인 제2클래드층(P-Al0.45GaAs)으로 이루어진 더블헤테로 구조(Double Heterostructure)층(2)을 형성하고 그 위에 두께가 30-100Å인 양자 우물층(언도프드 GaAs)(3)을 형성하고 다시 그 위에 제1 Si침투방지막(P-AlxGaAs(x≥0.6))(4)을 연속적으로 형성한다.2 shows a buffer layer (n-GaAs) / first cladding layer (n-Al0.) Having a thickness of 0.5 μm or more on the engine (n-GaAs) (1) as in the first embodiment of the present invention by MOCVD. A double heterostructure layer (2) formed of 45 GaAs) / active layer (undoped Al0.14 aAs) / second cladding layer (P-Al0.45GaAs) having a thickness of 0.2-0.65 μm and having a thickness thereon A quantum well layer (undoped GaAs) 3 having a thickness of 30 to 100 microseconds is formed, and a first Si penetration barrier film (P-AlxGaAs (x? 0.6)) 4 is continuously formed thereon.

여기서, 더볼헤테로 구조층(2) 대신에 버퍼층/제1클래드층(n-Al0.6GaAs)/제1그래드층(n-Al0.6 0.2GaAs)/활성 층(언도프드GaAs)/제2그래드층(P-Al0.2 0.6GaAs)/제2클래드층(P-Al0.6GaAs) 두께가 0.2∼0.65μm로 구성된 GRIN-SCH-SQW(Graded-Index Separate Confinement-Heterostructure Single Quantum Well)로 대체 가능하다.The buffer layer / first cladding layer (n-Al0.6GaAs) / first grade layer (n-Al0.6 0.2GaAs) / active layer (undoped GaAs) / second grade instead of the Duboltero structure layer 2 Can be replaced with GRIN-SCH-SQW (Graded-Index Separate Confinement-Heterostructure Single Quantum Well) consisting of 0.2-0.65μm thick layer (P-Al0.2 0.6GaAs) / second cladding layer (P-Al0.6GaAs) Do.

(B)와 같이 상기 제1 Si침투방지막(4)위에 SiO2 혹은 Si3N4의 절연막(6)을 PECVD 흑은 스퍼터로 증착한다.As shown in (B), an insulating film 6 of SiO 2 or Si 3 N 4 is deposited on the first Si penetration prevention film 4 by PECVD black sputtering.

(C)와 같이 상기 절연막(6)을 포토공정으로 폭이 일정길이(약 5-10μm)가 되도록 식각한 후 (D)와 같이 남겨진 절연막(6)에 전류제한층(8)을 MOCVD법으로 성장시켜 전류주입홈을 형성한다.The insulating film 6 is etched to have a predetermined length (about 5-10 μm) by the photo process as shown in (C), and then the current limiting layer 8 is removed by the MOCVD method on the remaining insulating film 6 as shown in (D). Growing to form a current injection groove.

이때, 전류주입홈의 모양은 웨이퍼의 방향에 따라 달라진다.At this time, the shape of the current injection groove varies depending on the direction of the wafer.

즉, 전류주입홈의 스트라이프 방향을 11 흑은 11로 하여 V모양으로 형성가능하다.That is, it is possible to form the V shape with the stripe direction of the current injection groove being 11 black or 11.

(E)와 같이 GaAs와 AlIGaAs의 선택적 에칭 용액인 HF에 담궈 절연막(6)과 제1 Si침투방지막(4)을 동시에 제거한다.As shown in (E), the insulating film 6 and the first Si penetration prevention film 4 are simultaneously removed by dipping in HF, which is a selective etching solution of GaAs and AlIGaAs.

(F)와 같이 제3클래드층(P-Al0.45GaAs)(9)과 캡층(P-GaAs)(10)을 MOCVD법으로 성장시킨다.As in (F), the third cladding layer (P-Al0.45GaAs) 9 and the capping layer (P-GaAs) 10 are grown by MOCVD.

이와같은 실시예에 있어서는 절연막(6)을 BoE로 식각하고 전류제한층(8)을 먼저 형성한후 제1 Si침투방지막(4)을 HF로 제거하기 때문에 포토공정이 간단하고 양자 우물층(3)이 가장 짧게 공기중에 노출되는 특징이 있으나 (E)에서 제1 Si침투방지막(4) 식각시 그 시간의 조절을 정확히 해야만 제1 Si침투방지막(4)의 전류제한층(8) 밑으로의 옆방향 침투를 제거할 수 있다.In this embodiment, since the insulating film 6 is etched with BoE and the current limiting layer 8 is formed first, and then the first Si anti-penetration film 4 is removed with HF, the photo process is simple and the quantum well layer 3 ) Is the shortest exposure to air, but in (E) the first Si penetration prevention film 4 must be precisely controlled at the time of the first Si penetration prevention film 4 below the current limiting layer 8. Lateral penetration can be eliminated.

제3도는 본 발명의 제2실시예이다. (A)의 공정은 제2도의 (A)와 동일하다. (B)와 같이 상기 제1 Si침투방지막(4)을 포토공정으로 폭(W2)을 갖도록 식각한 후 (C)와 같이 전면에 절연막(6)을 PECVD 혹은 스퍼터로 증착한다. 다음에 (D)와 같이 제1 Si침투방지막(4)과 같은 폭으로 BoE로 절연막(6)을 식각한다. 이때, BoE는 제1 Si침투방지막(4)을 식각하지는 못하므로 양호한 선택적 식각이 이루어진다. (E)와 같이 전류제한층(8)을 성장시켜 전류주입홈을 형성한다. (F)와 같이 GaAs와 AlGaAs의 선택적 식각용액인 HF에 담궈 절연막(6)과 잔여 제1 Si침투방지막(4)을 동시에 제거한다. (G)와 같이 제3클래드층(P-Al0.45GaAs)(9)과 캡층(P-GaAs)(10)을 MOCVD법으로 성장시킨다.3 is a second embodiment of the present invention. The process of (A) is the same as that of (A) of FIG. As shown in (B), the first Si penetration prevention film 4 is etched to have a width W2 by a photo process, and then the insulating film 6 is deposited by PECVD or sputter on the entire surface as shown in (C). Next, as shown in (D), the insulating film 6 is etched with BoE in the same width as that of the first Si penetration prevention film 4. At this time, since BoE does not etch the first Si penetration barrier 4, good selective etching is performed. As shown in (E), the current limiting layer 8 is grown to form a current injection groove. As shown in (F), the insulating film 6 and the remaining first Si penetration prevention film 4 are simultaneously removed by dipping in HF, which is a selective etching solution of GaAs and AlGaAs. As shown in (G), the third cladding layer (P-Al0.45GaAs) 9 and the capping layer (P-GaAs) 10 are grown by MOCVD.

이와같은 실시예에 있어서는 제1 Si침투방지막(4)을 먼저 HF로 식각하고 침투방지막(4)이 BoE에 식각되지 않는 특징을 이용하여 절연막(6)을 BoE로 식각하므로써 두층의 형태를 그대로 유지할 수 있게 된다.In such an embodiment, the first Si penetration barrier 4 is first etched with HF and the penetration barrier 4 is not etched in BoE, thereby maintaining the shape of the two layers by etching the insulation film 6 with BoE. It becomes possible.

제4도는 본 발명의 제3실시예이다. (A) 내지 (C)의 공정은 제2도의 (A) 내지 (C)의 공정과 거의 같으나 단지 제1 Si침투방지막(4)과 절연막(6) 사이에 제2 Si침투방지막(5)이 추가로 형성된 것이 다르며 여기서, 제1 Si침투방지막(4)으로는 P-Alz2GaAsz1-0.2를 사용하고 제2 Si침투방지막(5)으로 P-Alz1GaAs(zoO.6)을 사용한다. (D)와 같이 전표면에 포토레지스트(7)을 형성하여 이 포토레지스트(7)를 일정길이 (5-10μm)로 HF용액으로 제1,2 Si침투방지막(4)(5)을 단차지게 식각한다. 이때, 제1,2 Si침투방지막(4)(5)의 옆방향으로의 식각차는 0.25μm 정도로 제2 Si침투방지막(5)이 빠르게 식각된다.4 is a third embodiment of the present invention. The process of (A) to (C) is almost the same as the process of (A) to (C) in FIG. 2, except that the second Si penetration prevention film 5 is interposed between the first Si penetration prevention film 4 and the insulating film 6. In addition, P-Alz2GaAsz1-0.2 is used as the first Si penetration barrier 4 and P-Alz1GaAs (zoO.6) is used as the second Si penetration barrier 5. A photoresist 7 is formed on the entire surface as shown in (D), and the photoresist 7 is made to have a predetermined length (5-10 μm) by stepping the first and second Si penetration barriers 4 and 5 with HF solution. Etch it. At this time, the etching difference in the lateral direction of the first and second Si penetration barriers 4 and 5 is about 0.25 μm, so that the second Si penetration barrier 5 is etched quickly.

따라서, (E)와 같이 전류제한층(8)의 모양은 역 T자 모양으로 형성된다. (F)와 같이 전류제한층(8)을 형성하고 (G)와 같이 제1,2 Si침투방지막(4)(5)과 절연막(6)을 제거하며, 이때 전류제한층(8)이 역 T자 모양으로 형성되어 있어 전류제한층(8)의 에지(edge)에 존재할 수 있는 잔류 물질들을 효과적으로 제거할 수 있다. 다음에 (H)와 같이 제3클래드층(9), 캡층(10)을 MOCVD법으로 성장시킨다.Therefore, the shape of the current limiting layer 8 is formed in an inverted T shape as shown in (E). The current limiting layer 8 is formed as shown in (F), and the first and second Si penetration barriers 4 and 5 and the insulating film 6 are removed as shown in (G), wherein the current limiting layer 8 is reversed. It is formed in a T-shape to effectively remove residual materials that may be present at the edge of the current limiting layer 8. Next, as shown in (H), the third clad layer 9 and the cap layer 10 are grown by MOCVD.

제5도는 본 발명의 제4실시예이다. (A)공정은 제 4도(A)의 공정과 같으며 (B)와 같이 제1,2 Si침투방지막(4)(5)을 HF 용액에 식각하여 제1 Si침투방지막(4)의 폭과 제2 Si침투방지막(5)의 폭이 0.5 정도(양쪽 0.25μm)로 단차지게 한다. (C)와 같이 전면에 절연막(6)을 PECVD 흑은 스퍼터로 증착한다. (D)와 같이 절연막(6)을 BoE로 제1 Si침투방지막(4)의 폭과 같도록 식각하며, 이때 제1,2 Si침투방지막(4)(5)이 식각되지 않도록 한다. (E)와 같이 MOCVD법으로 전류제한층(8)을 형성하고 (F)와 같이 HF 용액으로 절연막(6)과 제1,2 Si침투방지라(4)(5)을 동시에 식각한다. (G)와 같이 제3클래드층(9)과 캡층(10)을 MOCVD법으로 성장시킨다.5 is a fourth embodiment of the present invention. The process (A) is the same as the process of FIG. 4A, and the width of the first Si penetration prevention film 4 is etched by etching the first and second Si penetration prevention films 4 and 5 into the HF solution as shown in (B). And the width of the second Si penetration barrier 5 is stepped to about 0.5 (0.25 μm on both sides). As shown in (C), the insulating film 6 is deposited on the entire surface by PECVD black sputtering. As shown in (D), the insulating film 6 is etched with BoE to be equal to the width of the first Si penetration prevention film 4, and the first and second Si penetration prevention films 4 and 5 are not etched. The current limiting layer 8 is formed by MOCVD as shown in (E), and the insulating film 6 and the first and second Si penetrant preventing layers 4 and 5 are simultaneously etched with HF solution as shown in (F). As shown in (G), the third clad layer 9 and the cap layer 10 are grown by MOCVD.

제6도는 본 발명의 제5실시예이다. (A)공정은 제 5도(A)와 동일하며 (B)와 같이 제1 Si침투방지막(4)위에 절연막(6)을 일정길이 (5-10μm)의 폭으로 식각한다. (D)와 같이 남겨진 절연막(6)에 전류제한층(8)을 MOCVD법으로 성장시켜 전류주입홈을 형성한다. (E)와 같이 GaAs와 AlGaAs의 선택적 식각용액인 HF에 담궈 절연막(6)과 제1,2 Si침투방지막(4)(5)을 동시에 제거한다. 다음에 (F)와 같이 제 3클래드층(9), 캡층(10)을 MOCVD법으로 성장시킨다.6 is a fifth embodiment of the present invention. The process (A) is the same as in FIG. 5A, and the insulating film 6 is etched on the first Si penetration prevention film 4 in a width of a predetermined length (5-10 μm) as shown in (B). The current limiting layer 8 is grown on the insulating film 6 left as in (D) by MOCVD to form a current injection groove. As shown in (E), the insulating film 6 and the first and second Si penetration barrier films 4 and 5 are simultaneously removed by dipping in HF, which is a selective etching solution of GaAs and AlGaAs. Next, as shown in (F), the third clad layer 9 and the cap layer 10 are grown by MOCVD.

제7도는 본 발명의 제6실시예로 모든 공정은 제6도와 같이 이루어지나 (D)와 같이 웨이퍼의 방향에 따라 전류주입홈의 모양이 달라지는 것을 나타낸 것이다.FIG. 7 shows a sixth embodiment of the present invention, in which all processes are performed as shown in FIG. 6, but as shown in (D), the shape of the current injection groove varies according to the direction of the wafer.

상기 제4도 내지 제7도의 실시예에서는 전류제한층(8)의 절연막(6)과 제1,2 Si침투방지막(4)(5)의 잔류물을 완전히 제거시킬 수 있는 특징을 갖는다.4 to 7, the residues of the insulating film 6 and the first and second Si penetration barrier films 4 and 5 of the current limiting layer 8 can be completely removed.

이상에서 설명한 바와같은 본 발명은 제1실시예와 같은 경우 포토공정이 간단하고 양자 우물층(3)이 가장 짧게 노출되는 효과가 있으며, 제2실시예와 같은 경우 제1,2 Si침투방지막(4)(5)을 먼저 HF로 식각한 후 BoE로 절연막(6)을 식각하여 제1,2 Si침투방지막(4)(5)과 절연막(6)의 형태로 그대로 유지할 수 있으며 제3실시예 내지 제6실시예와 같은 경우 전류주입홈 에지에 잔류하는 잔류물을 완전히 제거할 수 있는 효과가 있다.The present invention as described above has the effect that the photo process is simple and the quantum well layer 3 is exposed to the shortest in the case of the first embodiment, and in the case of the second embodiment, the first and second Si penetration barriers ( 4) (5) may be etched first with HF and then the insulating film 6 may be etched with BoE to maintain the first and second Si penetration barriers 4 and 5 and the insulating film 6 in the form of a third embodiment. In the case of the sixth embodiment, the residue remaining at the edge of the current injection groove can be completely removed.

Claims

A first process of sequentially forming a double hetero structure layer (2), a quantum well layer (3), and a first Si penetration prevention film (4) on the first conductive engine (1); and the first Si penetration prevention film (4). A second process of depositing an insulating film 6 thereon and selectively etching it to a predetermined width, a third process of growing a current limiting layer 8 in the remaining insulating film 6 to form a current injection groove, and the insulating film 6 ) And a fourth step of simultaneously removing the first Si penetration prevention film 4 and a fifth step of sequentially forming the third cladding layer 9 and the cap layer 10 on the entire surface. Method of manufacturing a laser diode.

The method of manufacturing a semiconductor laser diode according to claim 1, wherein the selective etching of the insulating film (6) uses BoE, and the removal of the insulating film (6) and the first Si penetration prevention film (4) uses HF.

A first process of sequentially forming a double hetero structure layer (2), a quantum well layer (3), and a first Si penetration prevention film (4) on the first conductive substrate (1), and the first Si penetration prevention film (4) A second step of selectively etching the second insulating film, a third step of forming the insulating film 6 on the entire surface and etching the same width as the remaining first Si penetration preventing film 4, and the etched insulating film 6 and the first Si A fourth process of forming a current injection groove by growing a current limiting layer 8 in the penetration barrier 4 and a quantum well layer by simultaneously removing the first Si penetration barrier 4 and the current limiting layer 8 And a sixth step of sequentially forming a third cladding layer (9) and a capping layer (10) on the entire surface thereof.

4. A method according to claim 3, wherein the first Si immersion prevention film (4) is first etched with HF and the insulating film (6) is etched with BoE.

A first step of sequentially forming a double hetero structure layer (2), a quantum well layer (3), a second Si penetration prevention film (5), and a first Si penetration prevention film (4) on the first conductive substrate (1); A second process of selectively depositing and insulating the insulating film 6 on the first Si penetration prevention film 4 and etching the first Si penetration prevention film 4 and the second Si penetration prevention film 5 by a photo process. However, the third step of forming a reverse T-shape by etching the width of the first Si penetration prevention film 4 to be shorter, and growing the current limiting layer 8 and the first and second Si penetration prevention films 4 and 5 And a fifth step of sequentially forming a third cladding layer (9) and a cap layer (10) on the entire surface of the semiconductor laser diode.

The first Si penetration prevention film 4 according to claim 5, wherein after the first step is performed, the first and second Si penetration prevention films 4 and 5 are etched stepwise to form an inverted T shape, and the insulating film 6 is covered to cover the first Si penetration prevention film 4. 4. The method of manufacturing a semiconductor laser diode, wherein the fourth and fifth processes are performed after etching the same as the width of?).

6. The method of claim 5, wherein after the first and second processes, the current limiting layer 8 is grown, and the insulating film 6 and the first and second Si penetration barrier films 4 and 5 are etched in an inverted T shape, A manufacturing method of a semiconductor laser diode, characterized by performing five steps.

The method of claim 7. A method of manufacturing a semiconductor laser diode, wherein the nitride film 6 is formed in the GaAs cross-section 11 directions.

The double hetero structure layer (2) according to any one of claims 1 to 7, characterized in that the double hetero structure layer (2) consists of a buffer layer / first cladding layer / active layer / second cladding layer having a thickness of 0.2 to 0.65 mu m. A method of manufacturing a semiconductor laser diode.

10. The GRIN-SCH-SQW according to claim 9, wherein a buffer layer, a first cladding layer, a first graded layer, an active layer, a second graded layer, and a second cladding layer are used instead of the double hetero structure layer (2). Method of manufacturing a semiconductor laser diode