KR960010073B1 - Semiconductor device and the manufacturing method thereof - Google Patents

Abstract

a first impurity diffusion region wherein a data storage node (7) is self aligned with a gate (6); a second impurity diffusion region wherein the data storage node is self aligned with a spacer (51) on the side wall of the gate (6), being the same conducting type with the first impurity diffusion region; a third impurity diffusion region which is formed below the second impurity diffusion region, being the opposite conducting type to the first impurity diffusion region.

Description

Semiconductor device and manufacturing method

1 is a circuit diagram of a stack random access memory cell.

2 and 3 are cross-sectional views of a static random access memory cell manufactured by a conventional method.

4 is a layout diagram of a static random access memory cell according to the present invention.

5 through 11 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to the method of the present invention when taken along the line A-A 'of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor memory device and a method of manufacturing the same having improved soft error rate (SER) by changing the structure of the data storage node.

Static random access memory (SRAM) is widely used in the medium and small-capacity memory fields because of its high speed and ease of use, although it is smaller in size than the dynamic random access memory (DRAM).

1 is a circuit diagram of a stack random access memory cell, comprising: an NMOS first transfer transistor formed at a left side of the cell and having a gate connected to a word line and a drain connected to a first bit line; An NMOS second transfer transistor formed at the right side of the cell, the gate of which is connected to the word line, and the drain of which is connected to a second bit line; An NMOS first driving transistor connected to a source of the first transfer transistor and a drain thereof, the source of which is grounded (V _ss ), and a gate of the first transfer transistor connected to a source of the second transfer transistor; An NMOS second driving transistor connected to a source of the second transfer transistor and a drain thereof, a source of which is grounded (V _ss ), and a gate of which is connected to a source of the first transfer transistor; A first load element having one side connected to a power supply terminal V _cc and the other side connected to a drain of the first driving transistor; And a stack random access memory cell having a second load element connected at one side thereof to a power supply terminal V _cc and at the other end connected to a drain of the second driving transistor. In FIG. 1, the first and second driving transistors and the first and second load elements constitute one flip flop.

In general, a memory cell of an SRAM is composed of two switching transistors and one flip-flop circuit. The storage information includes two nodes (the source of the first transmission transistor, the drain of the first driving transistor, the source of the first node A connected to the first load transistor, the source of the second transfer transistor, and the second node) that are the input / output terminals of the flip-flop. It is preserved by the voltage difference between the drain of the driving transistor and the second node B connected by the second load element. Actually, the stray capacitance at the two nodes (mainly the junction capacitance at the node A or B and the gate input capacitance) This charge is always replenished from the power supply V _cc through the load element, so that the memory information is not lost over time as in the case of a DRAM cell. In the flip-flop circuit that does not need a refresh function as time passes, the difference in signal charges of the two nodes when the information is read in the memory cell Width, so that large differential read signal is obtained does not have to sense amplifier as in the case of so without significantly affected by the noise DRAM.

SRAM having the above-mentioned advantages is a depletion load type using a depletion MOS transistor as a load element, a high resistance polycrystalline silicon load type using a high resistance polycrystalline silicon as a load element, and a PMOS thin film as a load element. It can be divided into a CMOS type using a transistor.

As the degree of integration of the device increases, the electric field in the device increases relatively, which causes hot carrier generation due to the high electric field, thereby lowering the reliability of the device. In the highly integrated SRAM, in order to solve the problem of lowering the reliability of the device due to hot carrier generation, the impurity diffusion regions (source and drain) constituting the transistor have a double structure (first impurity formed so as to self-align with the gate of the transistor. The second impurity diffusion region is formed so as to self-align with the diffusion region and the spacers formed on the sidewalls of the gate (called an LDD structure).

2 and 3 illustrate cross-sectional views of stack random access memory cells fabricated by conventional methods.

The gate and the second transfer of the first transfer 26 and drive 28 transistors (shown in Fig. 1) are formed on the semiconductor substrate on which the field oxide film 12 for dividing the semiconductor substrate 10 into active and inactive regions is formed. After the gates of the transistors of the driving and driving 30 transistors are formed, dopants of a conductivity type different from that of the semiconductor substrate (phosphorus ions in the case of NMOS transistors) are doped on the entire surface of the resultant, so that the gates The source 18 and drain 20 of the first transfer transistor matchedly formed, the source 24 and drain 18 of the first drive transistor, the source and drain of the second transfer transistor, and the second The source 22 and the drain 16 of the driving transistor (the impurity diffusion regions formed in the shape of self-alignment with the gate are referred to as a first water net diffusion region) are formed. Subsequently, an insulating material such as an oxide film is coated on the entire surface of the resultant to form a first insulating layer, and anisotropic etching is performed using the first insulating layer as an etching target to form spacers 32a on sidewalls of the gates. Second impurity diffusion regions 16a, 18a, and 20a which are self-aligned with the spacer by implanting impurities of a conductivity type different from that of the semiconductor substrate, for example, As ions, on the entire surface of the resultant material on which the spacer is formed. ) Is formed in each first impurity diffusion region. Subsequently, an insulating material such as an oxide film is applied to the entire surface of the resultant to form a second insulating layer 34 and partially remove the second insulating layer on the source of the first and second driving transistors. And a first constant power supply line (ground line) 36 in contact with the source of the second driving transistor. Subsequently, an insulating material such as an oxide film is applied to the entire surface of the resultant to form a third insulating layer 40 and partially remove the materials stacked on the impurity diffusion regions constituting the first and second nodes. By depositing and patterning a conductive material, such as polycrystalline silicon, the first and second load devices in contact with the first and second nodes, and partially connected to the first and second load devices constant power supply line of the second form a (V _cc power supply line) 44. Subsequently, an insulating material, such as an oxide film, is applied to the entire surface of the resultant to form a fourth insulating layer 46, and the second, third and fourth insulating layers on the drains of the first and second transfer transistors are partially formed. After removal, the first bit line 48 is in contact with the drain of the first transfer transistor and the second bit line 50 is in contact with the drain of the second transfer transistor by depositing and patterning a metal material such as aluminum. This completes the SRAM cell.

In the SRAM manufactured by the above-described conventional method, since the drain portion of the transistor serving as the data storage node has a normal LDD structure,? Particles penetrate and penetrate into the semiconductor substrate (electron hole pair (EHP)). In this case, the data storage junction, that is, a leakage path from the drain region of the transistor to the semiconductor substrate, generates a soft error. As a countermeasure, the concentration of the substrate is increased to reduce the diffusion width between the junction of the drain and the substrate. In this case, the potential barrier between the junctions is increased, so that the minority carriers generated in the substrate enter the storage node. This is suppressed. However, increasing the concentration of the substrate causes an overall synergistic effect of the cell transistor threshold voltage, which affects the operation of the device.

An object of the present invention is to provide a semiconductor device having an improved soft error rate without changing the characteristics of a conventional SRAM cell transistor.

Another object of the present invention is to provide a method for manufacturing a semiconductor device which can form the semiconductor device by an easy process.

A semiconductor device of the present invention for achieving the above object is a semiconductor in which the first and second transfer transistors, the first and second driving transistors, and the first and second load elements are interconnected to form a memory cell. 1. A memory device, comprising: a first impurity diffusion region having a source storage node connected to a source of the transfer transistor, a drain of the driving transistor, and a terminal of the load element formed in a shape that is self-aligned with a gate; A second impurity diffusion region of the same conductivity type as the first impurity diffusion region and a first impurity diffusion region formed under the first impurity diffusion region and the second impurity diffusion region formed in a shape that is self-aligned with a spacer And a third impurity diffusion region of the mold.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a memory cell includes a first and second transfer transistors, a first and a second driving transistor, and a first and a second load device connected to each other. A method of manufacturing a semiconductor memory device, comprising: forming gates of first and second transfer transistors and gates of first and second drive transistors on a semiconductor substrate; Forming a first impurity diffusion region by injecting impurities of a first conductivity type over the entire surface of the resultant material; Selectively opening only the first impurity diffusion region by a photolithography process using a photoresist to inject impurities of a second conductivity type to form a third impurity diffusion region under the first impurity diffusion region; Forming a spacer on the sidewalls of the gate by anisotropically etching the first insulating layer on the entire surface of the resultant material; And forming a second impurity diffusion region by injecting impurities of the first conductivity type into the entire surface of the resultant product.

As described above, in the semiconductor memory device of the present invention, a data storage node forms an impurity diffusion region of a conductivity type opposite to that of an impurity in the source and drain regions at a junction with a semiconductor substrate under the source and drain regions. It is characterized by a high concentration. Since there is no change in the overall concentration of the semiconductor substrate, there is no change in the characteristics of the cell transistor, and the depletion width of the depletion region of the junction becomes small.

Where W is the width of the depletion region, ε _{s is the} dielectric constant of the semiconductor, V _{bi is the} built-in potential, q is the magnitude of electronic charge, and N _{A is the} acceptor impurity density. _j : each shows junction capacitance.)

As can be seen from the above equation, the capacitance becomes large, and

(Wherein K: Boltzmann constant, T: absolute temperature, N _D : donor impurity density, N _i : intrinsic impurity density, respectively).

As can be seen from the above equation, the potential barrier between the junction, that is, N ⁺ / P ^_ , becomes high. These results not only prevent the inflow of the minority carriers to the storage node generated on the substrate, but also reduce the probability of causing soft errors due to the high capacitance of the node-end junctions.

The process of forming an impurity diffusion region having a conductivity type opposite to that of the impurities in the source and drain regions on the junction portion of the data storage node with the semiconductor substrate under the source and drain regions is performed by the PMOS transistors in the peripheral circuit portion other than the merery cell region. It is formed together during the P-LDD forming process (when the memory cell transfer and drive transistor are NMOS), and the process is not added.

Therefore, according to the present invention, the characteristics of the cell transistors are not changed, and the soft error rate can be improved without using a separate mask.

Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail.

4 shows the layout of the static random access memory cell according to the present invention. In the drawing, reference numeral 101 denotes a mask pattern for forming an active region, and reference numeral 102 denotes a mask pattern for forming gates of the first and second transfer transistors and gates of the first and second driving transistors. Reference numeral 103 denotes a mask pattern for a P-type impurity diffusion region, which is a third impurity diffusion region, between the source and drain regions of the first and second impurity diffusion regions, which are data storage nodes, and the semiconductor substrate. In addition, reference numeral 106 denotes a contact hole for contacting the first constant power line to the source region of the driving transistor and a mask pattern for forming a contact hole for contacting the drain to the drain of the transfer transistor and a pattern to contact the bit line. Reference numeral 107 denotes a mask pattern for forming a first electric power line and a mask pattern for forming a pad to be in contact with the bit line, and reference numeral 104 denotes a first and a second load element. A mask pattern for forming a contact hole for contacting the node end is shown. Reference numeral 105 denotes a mask pattern for forming first and second load elements and a second constant power line, and reference numeral 108 denotes a contact hole for contacting the first and second bit lines to the pad. A mask pattern for formation is shown, and reference numeral 109 denotes a mask pattern for bit line formation.

Next, a manufacturing method of the semiconductor memory device of the present invention using each mask pattern shown in FIG. 4 will be described with reference to FIGS. 5 through 11 are cross-sectional views taken along the line A-A 'of the layout of FIG. 4; first, referring to FIG. 5, a transfer and drive transistor constituting an SRAM is applied to the P-type semiconductor substrate 1; In case of forming NMOS transistor, the semiconductor substrate is divided into an active region and an inactive region by oxidizing the substrate by a selective oxidation method (LOCOS) using the mask pattern for forming the active region (reference numeral 101 in FIG. 4). After the field oxide film 2 is formed, an ion implantation process for adjusting the threshold voltage is performed. Subsequently, a high quality oxide film to be used as the gate oxide film 3 is formed on the entire surface of the semiconductor substrate where the active region and the inactive region are separated by the field oxide film 2, for example, by using an oxidation process such as a dry oxidation method. As a first conductive layer for forming the gates of the first and second transfer transistors and the gates of the first and second driving transistors, for example, polycrystalline silicon or polycrystalline silicon 4 and silicide 5 are laminated (6) After deposition, a photolithography process is performed using a mask pattern (reference numeral 102 in FIG. 4) for forming gates of the first and second transfer transistors and gates of the first and second driving transistors. The gate and the gate of the driving transistor are formed. The above process is the same as the conventional process.

Next, referring to FIG. 6, the source and drain of the first and second transfer transistors and the first and second driving transistors may be doped with N-type impurities such as P (Phosphorus) ions at a low concentration on the entire surface of the resultant. (7) is formed.

Next, referring to FIG. 7, a photoresist PR is coated on the entire surface of the resultant, and then a mask pattern for forming a P-type impurity region is formed between the source and drain regions, which are the data storage nodes, and the semiconductor substrate. The photoresist PR is patterned by a photolithography process using reference numeral 103, followed by ion implantation of P-type impurities such as B or BF ₂ to form the P-type impurity region 8. This process is performed in the P-type impurity ion implantation process for forming the P-LDD structure of the PMOS transistor (not shown) formed in the peripheral circuit portion other than the memory cell region. In the conventional case, the peripheral circuit portion In ion implantation for forming a P-type impurity region of a PMOS transistor, a P-type impurity was implanted only in a predetermined portion of the peripheral circuit portion after covering the memory cell region with a photoresist or the like. During ion implantation for a P-type impurity region of a transistor, a predetermined portion of a source and drain region, which is a data storage node, is opened so that P-type impurity is implanted. Therefore, a P-type impurity region can be formed between a source and drain region, which is a data storage node, and a semiconductor substrate without an additional process.Isolation of P-type impurities into an NMOS transistor improves isolation characteristics and prevents leakage current. A side effect is also obtained in which the properties are also improved.

Subsequently, referring to FIG. 8, a first insulating layer is formed on the resultant, and then anisotropically etched to form spacers 51 on sidewalls of the gate 6 of the transfer transistor and the driving transistor.

Subsequently, an N-type impurity such as As ion is ion-implanted on the entire surface of the resultant on which the spacer 51 is formed to form a high concentration source and drain region 9 having a shape that self-aligns with the spacer.

Next, referring to FIG. 9, after forming the second insulating layer 52 on the entire surface of the resultant, for example, using an insulating material such as an oxide film, the first and second load devices may be replaced with the first and second load elements. A photolithography process is performed using the mask pattern (reference numeral 104 in FIG. 4) for forming a contact hole for contacting the node end by using the first insulating layer as an object to be etched. 9) and a contact hole exposing the first and second node ends. Subsequently, for example, after depositing polysilicon 54 as a second conductive layer on the entire surface of the semiconductor substrate where the contact hole is formed, a mask pattern for forming the first and second load elements and the first constant power line A photolithography process using reference numeral 105 in FIG. 4 is performed to form first and second load elements and first constant power supply line 54.

Next, referring to FIG. 10, a third insulating layer 55 may be coated by applying an insulating material, for example, a single layer of an oxyhydroxide layer or a composite layer in which a pure oxide layer and an insulating material doped with impurities are laminated. ), The contact hole (reference numeral 106 'in FIG. 4) for contacting the second constant power line to the source region of the driving transistor, the source of the first transfer transistor, and the drain of the second driving transistor A mask pattern for forming a contact hole for connecting a contact hole (reference numeral 106 in FIG. 4) and a pad contacting the bit line to the drain of the transfer transistor, which may be connected using a gate conductive material of a driving transistor A photolithography process using reference numeral 106 in Fig. 4 is performed to form contact holes on the source (7, 9) of the driving transistor, the drain of the transfer transistor, and the drain of the second driving transistor. . Subsequently, a third conductive layer is deposited on the entire surface of the semiconductor substrate on which the contact hole is formed, for example, polysilicon or a conductive material in which polysilicon and silicide are laminated, and then a mask pattern and a bit line for forming a second constant power line. A photolithography process using a mask pattern for forming a pad in contact with the mask and a mask pattern (reference numerals 107, 107 ', 107 in FIG. 4) for forming a portion connecting the first transfer transistor, the second driving transistor, and the drain. The second constant power line (not shown), the pad 58 'and the connecting portion 58 are formed.

Next, referring to FIG. 11, after the fourth insulating layer 59 is formed by coating an entire surface of the resultant, for example, a pure oxide film or an insulating material in which a pure oxide film and an impurity-doped insulating material are laminated. A photolithography process was performed using a mask pattern (reference numeral 108 in FIG. 4) for forming a contact hole for contacting the first and second bit lines to the pad to form a contact hole on the pad. After depositing a conductive material, for example, a metal material such as aluminum, a photolithography process using a mask pattern (reference numeral 109 in FIG. 4) for forming a bit line is performed to fill the contact hole to connect to the semiconductor substrate through the pad. The bit line 61 is formed.

In the above embodiment, the polysilicon of the fixed term is used as the load element, but the deflation type transistor and the PMOS thin film transistor described above may also be used as the load element.

As described above, according to the present invention, a semiconductor memory device in which the soft error rate is improved and the insulation characteristics of the cell transistor is improved without changing the cell transistor characteristics in an easy process without additional steps is realized.

The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical idea of the present invention.

Claims (10)

A semiconductor memory device in which first and second transfer transistors, first and second drive transistors, and first and second load devices are connected to each other to form a memory cell, wherein the source and the source of the transfer transistor are the same. The data storage node connected to the drain of the driving transistor and one terminal of the load element may have a first impurity diffusion region formed in a shape that is self-aligned with a gate and a self-aligned shape with a spacer formed in the sidewall of the gate. And a second impurity diffusion region of the same conductivity type as the impurity diffusion region, and a third impurity diffusion region of the opposite conductivity type to the first impurity diffusion region formed under the first impurity diffusion region and the second impurity diffusion region. A semiconductor memory device. The semiconductor memory according to claim 1, wherein the first impurity diffusion region and the second impurity diffusion region are simultaneously formed in a shape that is self-aligned with the gate when the source and the drain of the NMOS transistor constituting the memory cell are formed. Device. The semiconductor memory device according to claim 1, wherein the third impurity diffusion region is formed at the same time as the source and the drain of the PMOS transistor of the peripheral circuit portion which do not constitute the memory cell. The semiconductor memory device according to claim 1, wherein the concentration of the third impurity diffusion region is higher than the concentration of the first impurity diffusion region and the second impurity diffusion region is lower than the concentration. The semiconductor memory device according to claim 1, wherein the load element is formed of any one selected from a PMOS thin film transistor and a high resistance polycrystalline silicon. A semiconductor memory device in which a first and a second transfer transistor, a first and a second driving transistor, and a first and a second load element are connected to each other to form a memory cell, Forming gates of the first and second transfer transistors and gates of the first and second drive transistors; Forming a first impurity diffusion region by injecting impurities of a first conductivity type into the entire surface of the resultant material; Selectively opening only the first impurity diffusion region by a photolithography process using a photoresist to inject impurities of a second conductivity type to form a third impurity diffusion region under the first impurity diffusion region; Forming a spacer on the sidewalls of the gate by anisotropically etching the first insulating layer on the entire surface of the resultant material; And forming a second impurity diffusion region by injecting impurities of a first conductivity type into the entire surface of the resultant material. The method of manufacturing a semiconductor memory device according to claim 6, wherein polycrystalline silicon or a conductive material in which polysilicon and silicide are laminated is used as a material for forming a gate of the transfer transistor and the driving transistor. 7. The method of manufacturing a semiconductor memory device according to claim 6, wherein P is used as an impurity of a first conductivity type forming said first impurity diffusion region. The method of manufacturing a semiconductor memory device according to claim 6, wherein As is used as an impurity of a first conductivity type forming said second impurity diffusion region. The method of manufacturing a semiconductor memory device according to claim 6, wherein any one selected from B and BF ₂ is used as an impurity of the second conductivity type forming said third impurity diffusion region.