KR960007674B1 - Atm switch with nonsymmetric and constrained common memory - Google Patents

Abstract

k number of input means 16 having a plurality of series/parallel converters 17; a shared memory section 22 having k number of sub-shared memory section 32 connected to the input means 16; a control means 34 for controlling the shared memory 22; a demultiplexing means 20 for demultiplexing the output of the shared memory 22; and a plurality of parallel/series converting means 21 for converting the parallel output of the demultiplexing means 20 into a series data; a plurality of routing decoding means 35; a plurality of a first buffer means 36; a plurality of running-add network 39; multiple debanian network 40; a first multiplexing means 42; and a plurality of a phase address fool 37.

Description

Asymmetrical Limited Shared Memory Asynchronous Transfef (ATM) Switch Device

1 is a diagram illustrating a conventional (N × N) switch.

2 is an asymmetric switch configuration based on an existing circuit (m × n).

3 is a block diagram according to the present invention.

4 is a configuration diagram of a common memory unit according to the present invention.

5 is a block diagram of a control unit according to the present invention.

6 is a diagram illustrating one embodiment of a running Ed network and an inverse Banyan network according to the present invention.

7 is an address format diagram of a control unit according to the present invention.

8 is an inlet cell format diagram of the present invention.

The present invention relates to an m × n asymmetric limited asynchronous transfer mode (ATM) switch device.

ATM is in the spotlight as an important means of realizing transmission and switching in the construction of the broadband integrated telecommunication network, and specific standards are being developed for realization by the International Telegraph and Telephone Advisory Committee (CCITT). Major aspects of ATM development include switch structure, protocol structure, and traffic control technology. Among them, ATM switch structure has been actively presented with various switches to date.

There is also a great variety of methods for classifying these switches, which are classified into input buffer type, output buffer type and internal buffer type according to the position of the buffer, and are classified according to the actual switch realization methods. Each is classified into a type.

However, these switches can be roughly classified into two types today.

First, Starlite Switch, Sunshine Switch Baseline developed based on the interconnection network, which was studied to interconnect multiple processors and memory modules in the late 60s. Second, SBMS (Shared Buffer Memory Switch), Prelude Switch, ATOM (ATM Output Buffer Modulr) Switch, etc., which is based on the time division time switch used in the traditional digital circuit switched switch. .

ATM switches are being considered for use as public networks as well as local area networks (LANs) around the world.

1 is a conventional (N × N) switch diagram, and FIG. 2 is a (m × n) asymmetric switch diagram based on a basic circuit, where 1 and 8 are serial / parallel converters, and 2 and 9 are multiplexers. 3 and 10 are common memories, 4 and 11 are controllers, 5 and 12 are demultiplexers, and 6 and 13 are parallel to serial converters, respectively.

Most of the advanced countries use the shared memory type switch as shown in FIG. 1 due to hardware efficiency and economical efficiency when configuring a large capacity ATM switch. These switch structures are generally symmetrical (N × N) switch structures with the same input and output scales, where the operating speed v of the time division multiplexing bus 7 of FIG. 1 is the number of input ports (N) and the serial / parallel converter According to the number of outputs (1) in (1) and the input data rate (r bits / sec), the following equation 1 is used.

v = rN / P (bit / sec) ..................... .............(One)

The operating speed v of the time division multiplexing bus 7 determines the operating speed of the shared buffer memory switch of FIG. 1, and as shown in Equation 1, as the operating speed increases in proportion to the number of input ports N, It has been pointed out as a problem when manufacturing an integrated circuit (VLSI).

Meanwhile, the growable switch proposed by K.Y.Eng et al. Or K.H. The number of input ports (m) is shown in Fig. 2 when the conventional shared memory switch shown in Fig. 1 is used for the (m × n) asymmetric ATM switch used in the two-stage structure switch proposed by Kang et al. The speed of the input time-division multiplexed bus 14 is relatively fast compared to the output time-division multiplexed bus 15 so that the overall switching speed depends on the input time-division multiplexed bus 14 as it is relatively large relative to the number n. Therefore, when the number of input ports (m) is more than twice as large as the number of output ports (n), the overall switching speed is increased by more than twice, which causes difficulties in manufacturing a large integrated circuit (VLSI).

Accordingly, the present invention provides an asymmetric limited shared memory asynchronous transfer mode switch having a switching operation speed that depends on n relatively small compared to m when the input (m) and the output (n) are different from each other. The purpose is to provide a device.

In order to achieve the above object, the present invention, k input means consisting of a plurality of serial / parallel converters received by grouping m inputs k (k = m / n) (m, n, k is a natural number); A common memory having k sub-common memory parts connected to the input means, respectively; Control means for controlling the common memory unit; Demultiplexing means for demultiplexing the output of the common memory unit; And a plurality of parallel / serial conversion means for receiving the parallel outputs of the demultiplexing means and converting them in series, wherein the control means receives and decodes cell routing information from each of the sub-common memory units. Decoding means; A plurality of first buffering means for receiving and outputting a pause address after being enabled according to the output of the routing decoding means; A plurality of running ED networks that receive the output of the first buffering means and add an output address before the routing information cell; A plurality of inverse Banian networks that receive the outputs of the running ED networks and store them in an output address FIFO in the order of arrival addresses; First multiplexing means for receiving and outputting the output of the bag; And a plurality of idle address pools receiving the output of the first multiplexing means through a first address filter and outputting the first buffering means and the sub common memory unit.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention;

Initially, k idle address pools ₁ (i = 1, 2, ... k) 37 of FIG. 5 are filled with the addresses of k common memories ₁ 25 of FIG. At this time, the idle address pool 1 37 corresponds to each common memory ₁ 25. Meanwhile, as shown in FIG. 7, these control unit addresses are group log bits consisting of [log ₂ k] to distinguish k groups from each other and [log ₂ Bi corresponding to the scale Bi of each common memory i 25. It consists of an address bit string consisting of].

Further, k ^* n output addresses FIFOij 41 (i = 1, 2, ..., kj = 1, 2, ..., n) in FIG. 5 are cleared and become empty. After this series of initialization processes, normal switch operation is achieved.

The input cell format of FIG. 3 includes routing information bits consisting of cell information to be exchanged as shown in FIG. 8 and [log ₂ n] for self routing information in the switch. Each of these input cell streams is converted into p parallel data streams 18 by serial / parallel converter 17 and input to common memory and control unit 19, as shown in FIG. At this time, the number of input ports (m) is k (k = [m / n]) input ports (m, n, k are natural numbers as shown in FIG. 3 in order to reduce the operation speed of the common memory of FIG. 4). Grouping into sub-blocks 16 is input to k sub-common memory sections 32 as shown in FIG.

Therefore, the common memory section 22 of FIG. 4 is composed of k sub-common memory sections 32, and the speed of the input time division multiplexing bus 33 is the same as the output time division multiplexing bus 27, so that the input port number m Regardless, it is possible to manufacture a large scale integrated circuit (VLSI) by operating at a speed of v = rn / p [bps] corresponding to the number n of output ports.

Meanwhile, the parallel data stream 18 of FIG. 4 is time-division multiplexed by the multiplexer 23, and the input port P 18 is connected to the input time-division multiplexed bus 33 of the [p / n] -th sub-common memory unit 32. FIG. The p '{p' = pn ([b / n] -1)} th cell timeslot is occupied. During the p'-th cell timeslot (p '= 1, 2, ..., n) on the input time division multiplexing bus 33, two types of operations, namely writing and reading operations of the common memory 25, are performed.

The routing information of the p'-th cell timeslot is latched by the latch 24 and transmitted to the routing decoder 35 of the controller of FIG. 5 as shown in FIG.

The routing decoder 35 of the control unit of FIG. 5 receives and decodes the p'-th cell routing information received from the common memory unit 22 of FIG. 4 so that the p'-th cell of the n buffers 36 is output. The output port buffer 36 is enabled. At this time, the idle address shown in FIG. 7 which is waiting for the idle address pulli is sent to the running ED network 39 through the enabled buffer, and simultaneously through the write address bus 30 in [p / n] th sub-common memory unit 25. On the other hand, such a series of operations are performed at the same time for each k sub-blocks so that when the k sub-common memory unit 32 is directed to the same output port at the same time to meet the non-blocking conditions for the running ED network 39, reverse It consists of an eye network 40 and k output addresses FIFOij 41.

One embodiment of the (8 × 8) scale of the running Ed network 39 and the inverse Banian network 40 is shown in FIG.

The running ED network of FIG. 6 attaches an output address ([a + S] modular n) to the routing information cell when the input 43 has routing information. Thus, due to the nature of the inverse Banian network 40, the address packets of the controller are sequentially stored from the top to the bottom, in the order of addresses arriving at the k output addresses FIFOij 41 in a round-robin manner.

The read operation of the j-th (j = 1, 2, ... n) cell timeslot of the read address bus 31 of FIG. 5 moves a cell destined for the output port j out of k common memories 25 out of the read address bus ( 31, the group identifier bit string and the address filter 28 in the read address as shown in FIG. 7 are read from the common memory 25 selected from the same sub common memory section 32, and the demultiplexer 20 of FIG. The output signal is sent to the output port j through the serial converter j23.

On the other hand, in order to send k sub-common memory sections 32 to one output time division multiplexing bus 27, each sub-common memory section 32 is connected through a buffer 26 and these buffers 26 are read. It is enabled when the group identifier bit string and the address field in the address format are the same.

The read addresses on the read address bus 31 used for the read operation of the j-th cell timeslot are k idle address pools 37 through the corresponding address filter 38 in the controller 34 for use as the write address again. It is stored in one of the idle address pool 37.

The address on the read address bus 31 is time-division multiplexed by the multiplexer based on the output addresses FIFOi, j based on j (jj = 1, 2… n), and each output address FIFOij is i (i = 1) for each multiplexing period n. The addresses stored in each output address FIFOij are sequentially read in a round-robin manner based on, 2, ... k), thereby ensuring cell order integrity.

Claims (3)

k input means (16) consisting of a plurality of serial / parallel converters (17) which receive m input by grouping m inputs into k (k = m / n) (m, n, k are natural numbers); A common memory section 22 having k sub-common memory sections 32 connected to the input means 16, respectively; Control means (34) for controlling the common memory section (22); Demultiplexing means (20) for receiving and demultiplexing the output of the common memory unit (22); And a plurality of parallel / serial converting means 21 for receiving the parallel outputs of the demultiplexing means 20 and converting them in series, wherein the control means 34 are each sub-common memory unit 32. A plurality of routing decoding means (35) for receiving and decoding cell routing information from the apparatus; A plurality of first buffering means (36) for receiving and outputting a pause address after being enabled according to the output of the routing decoding means (35); A plurality of running ED networks 39 for receiving an output of the first buffering means 36 and adding an output address before the routing information cell; A plurality of inverse Banian networks 40 which receive the outputs of the running ED network 39 and store them in the output address FIFO 41 in the order of arrival addresses; First multiplexing means (42) for receiving and outputting the output of the cover (41); And a plurality of idle address pools 37 which receive the output of the first multiplexing means 42 through the first address filter 38 and output the first buffering means 36 and the sub common memory unit 32. Asymmetric limited asynchronous transfer mode switch device characterized in that it comprises a). 2. The control means (34) according to claim 1, wherein said control means (34) includes a group identifier bit sequence and uses an address format for separately handling a plurality of western common memory portions (320) using these bit sequences and the first address field (38). Asymmetric limited asynchronous transfer mode switch device, characterized in that configured to use. The sub common memory section (32) comprising the common memory section (22) comprises: second multiplexing means (32) for time-division multiplexing the parallel data streams from the input means (16); Latch means (24) for receiving the routing information from the second multiplexing means (23) and latching it to output the routing decoding means (35); The first multiplexing means 42 receives the read address through the second address filter 28 and the second multiplexing means 23 stores the output data or receives the write address from the idle address pool 37. A common memory 25 for outputting data; And a second buffering unit configured to receive the read address of the first multiplexing means 42 through the second address filter 28 and to enable the output of the common memory 25 to the demultiplexing means 20. Asymmetric limited asynchronous delivery mode switch device, characterized in that it comprises a means (26).