KR960007099Y1

KR960007099Y1 - Reference voltage source circuit

Info

Publication number: KR960007099Y1
Application number: KR2019960013034U
Authority: KR
Inventors: 히로시 요시노
Original assignee: 가부시키가이샤 도시바; 아오이 죠이치; 도시바 마이크로 일렉트로닉스 가부시키가이샤; 다케다이 마사다카
Priority date: 1990-06-22
Filing date: 1996-05-23
Publication date: 1996-08-19

Abstract

요약없음No summary

Description

Reference voltage source circuit

제1도는 본 고안의 제1실시예를 나타낸 회로도1 is a circuit diagram showing a first embodiment of the present invention

제2도는 본 고안의 제2실시예를 나타낸 회로도2 is a circuit diagram showing a second embodiment of the present invention

제3도와 제4도는 각각 종래의 기준전압원회로를 나타낸 회로도이다3 and 4 are circuit diagrams showing conventional reference voltage source circuits, respectively.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11, 11a : 기준전압원회로12, 12a : 증폭회로11, 11a: reference voltage source circuit 12, 12a: amplification circuit

14 : 차동쌍Q11, Q12 : PNP 트랜지스터14: differential pair Q11, Q12: PNP transistor

Q15 : NPN 트랜지스터Q16 : NPN 트랜지스터Q15: NPN transistor Q16: NPN transistor

Q17 : PNP 트랜지스터Q17: PNP transistor

[산업상의 이용분야][Industrial use]

본 고안은 예컨대 바이폴라 모놀리식 집적회로에 사용되는 기준바이어스 전원회로에 관한 것으로, 특히 역다링톤접속된 증폭회로의 전류바이어스를 결정하기 위해 사용되는 기준바이이어스 전원회로에 관한 것이다.The present invention relates to a reference bias power supply circuit for use in, for example, a bipolar monolithic integrated circuit, and more particularly, to a reference bias power supply circuit used to determine a current bias of an inverse ring ring connected amplification circuit.

[종래의 기술 및 그 문제점][Traditional Technology and Problems]

제3도는 종래의 역다링톤접속된 증폭단의 전류바이어스회로를 나타낸 도면으로, 소정 전압(Vcc)이 공급되는 전원단자(20)에는 기준전압원회로(21)와 증폭회로(22)가 접속되어 있다. 상기 기준전압원회로(21)에 있어서, 일단이 상기 전원단자(20)에 접속된 전류원(Iref)의 타단에는 다이오드접속된 NPN트랜지스터(Q1)의 콜렉터·베이스가 접속되어 있고, 이 NPN트랜지스터(Q1)의 에미터는 접지되어 있는 한편 베이스는 저항(Ri)을 매개해서 증폭회로(22)를 구성하는 NPN트랜지스터(Q2)의 베이스에 접속되어 있으며, 이 NPN트랜지스터(Q2)의 베이스에는 결합용량(Ci)을 매개해서 신호원(Vi)이 접속되어 있다.3 is a diagram showing a conventional current bias circuit of an amplifying stage connected to a reversed ring tone. A reference voltage source circuit 21 and an amplifier circuit 22 are connected to a power supply terminal 20 to which a predetermined voltage Vcc is supplied. In the reference voltage source circuit 21, a collector base of a diode-connected NPN transistor Q1 is connected to the other end of the current source Iref, one end of which is connected to the power supply terminal 20, and the NPN transistor Q1. Emitter is grounded, while the base is connected to the base of the NPN transistor Q2 constituting the amplifying circuit 22 via a resistor Ri. The base of the NPN transistor Q2 has a coupling capacitance Ci. The signal source Vi is connected via the.

상기 증폭회로(22)에 있어서, NPN트랜지스터(Q2)의 콜렉터에는 다이오드접속된 트랜지스터(Q3)의 베이스와 콜렉터가 접속되어 있고, 이 트랜지스터(Q3)의 에미터는 상기 전원단자(20)에 접속되어 있는 한편 그 트렌지스터(Q3)의 베이스는 PNP트랜지스터(Q4)의 베이스에 접속되어 있다. 상기 트랜지스터(Q4)의 에미터는 상기 전원단자(20)에 접속되어 있고, 그 콜렉터는 출력단자(23)에 접속되어 있음과 더불어, 저항(R_L)을 매개해서 접지되어 있다. 여기서, 상기 트랜지스터(Q1, Q2; Q3, Q4)는 각각 전류미터(current mirror) 회로를 구성하고 있다.In the amplifier circuit 22, the collector of the NPN transistor Q2 is connected to the base of the transistor Q3 connected to the collector, and the emitter of the transistor Q3 is connected to the power supply terminal 20. On the other hand, the base of the transistor Q3 is connected to the base of the PNP transistor Q4. The emitter of the transistor Q4 is connected to the power supply terminal 20, the collector of which is connected to the output terminal 23, and grounded via a resistor R _L. Here, the transistors Q1 and Q2; Q3 and Q4 each constitute a current mirror circuit.

상기한 구성에 있어서 트랜지스터(Q1, Q2)와 트랜지스터(Q3, Q4)의 전기적 특성이 일치되고 있으므로 각 트랜지스터의 전류이득이 어느 정도 높은 경우 안정된 바이어스전류를 설정할 수 있다.In the above configuration, since the electrical characteristics of the transistors Q1 and Q2 and the transistors Q3 and Q4 coincide, stable bias current can be set when the current gain of each transistor is high to some extent.

일반적으로 저전압동작을 목적으로 하는 전류증폭단으로서의 증폭회로는 상기와 같이 NPN트랜지스터(Q2)와 PNP트랜지스터(Q4)을 다링톤접속한 소위 역다링톤구성으로 되어 있고, 또 사용하는 트랜지스터의 전류이득의 변동을 고려해서 트랜지스터(Q4)에 트랜지스터(Q3)를 접속하여 전류미러회로를 설계해 주고 있다.In general, the amplifying circuit as the current amplifier stage for the purpose of low voltage operation has a so-called reverse darling tone configuration in which the NPN transistor Q2 and the PNP transistor Q4 are connected to Darlington as described above, and the current gain of the transistor used is varied. In consideration of this, the current mirror circuit is designed by connecting the transistor Q3 to the transistor Q4.

2개의 트랜지스터를 다링톤접속한 경우, 단일의 트랜지스터의 경우에 비해 전류이득이 2배로 되게 되지만, 상기 회로와 같이 트랜지스터(Q2, Q4)의 상호간에 트랜지스터(Q3)가 접속되어 있는 경우, 전류이득을 높게 할 수 없는 경우가 있다.When two transistors are connected in Darlington, the current gain is doubled as compared with the case of a single transistor. However, when the transistors Q3 are connected to each other of the transistors Q2 and Q4 as in the circuit described above, the current gain is increased. You may not be able to make it higher.

그래서, 전류이득을 높게 하기 위해 제4도에 도시된 바와 같이 트랜지스터(Q3)의 에미터와 같이 전원(Vcc)사이에 저항(R)을 삽입하여 신호 전류에 따라 트랜지스터(Q3, Q4)로 구성된 전류미러회로의 전류이득을 증가 시키는 구성이 고려되고 있지만, 이 경우 입출력특성이 선형으로 되지 않기 때문에 왜곡성분이 증가된다는 문제가 있다.Thus, in order to increase the current gain, as shown in FIG. 4, a resistor R is inserted between the power supply Vcc, as shown in the emitter of the transistor Q3, and the transistors Q3 and Q4 are configured according to the signal current. Although a configuration for increasing the current gain of the current mirror circuit has been considered, in this case, there is a problem that the distortion component is increased because the input / output characteristics are not linear.

[고안의 목적][Purpose of designation]

본 고안은 상기한 점을 감안하여 안출된 것으로, 높은 전류이득을 가지면서 왜곡성분이 감소된 다링톤접속의 전류증폭단의 바이어스가 가능한 기준전압원회로를 제공함에 그 목적이 있다.The present invention has been made in view of the above, and an object thereof is to provide a reference voltage source circuit capable of biasing the current amplification stage of a Darlington connection having a high current gain and a reduced distortion component.

[고안의 구성][Composition of design]

상기 목적을 달성하기 위한 본 고안은, 출력단에 연결된 콜렉터를 갖춘 제1도전형의 제1트랜지스터와 입력신호가 베이스에 공급되는 제2도전형의 제2트랜지스터를 포함하는 역달링톤회로에 바이어스전류를 공급하기 위한 기준전압원회로가, 각각 베이스와, 콜렉터 및, 정전류에 의해 바이어스되는 에미터를 갖춘 상기 제1도전형의 제3 및 제4트랜지스터를 포함하고, 상기 제2트랜지스터가 상기 제3 및 제4트랜지스터의 각 에미터영역의 정수배인 에미터영역을 갖는 차동증폭기와, 기준전위를 발생시키기 위해 상기 제3트랜지스터의 베이스에 연결된 기준 전위회로 및 각각 베이스와, 상기 제3 및 제4트랜지스터의 콜렉터에 각각 연결된 콜렌터 및, 에미터를 갖추고, 상기 기준전위회로에 의해 발생된 기준전위에 따라 상기 제4 및 제2트랜지스터의 베이스를 제어하는 상기 제2도전형의 제5 및 제6트랜지스터를 포함하는 전류미러회로를 구비하여 구성된 것을 특징으로 한다.The present invention for achieving the above object, the bias current in the reverse Darlington circuit comprising a first transistor of the first conductivity type having a collector connected to the output terminal and a second transistor of the second conductivity type, the input signal is supplied to the base A reference voltage source circuit for supplying a first transistor comprising a third and a fourth transistor of the first conductivity type having a base, a collector, and an emitter biased by a constant current, respectively, wherein the second transistor comprises the third and the third transistors; A differential amplifier having an emitter region that is an integer multiple of each emitter region of the fourth transistor, a reference potential circuit connected to a base of the third transistor to generate a reference potential, and a base, respectively, of the third and fourth transistors; A base of the fourth and second transistors having a collector connected to the collector and an emitter, respectively, in accordance with the reference potential generated by the reference potential circuit. By a current mirror circuit including fifth and sixth transistors of the second conductivity type which is characterized in that control is configured.

(작용)(Action)

상기와 같이 구성된 본 고안은, 공통에미터가 정전류원에 의해 바이어스되는 차동쌍 트랜지스터의 콜렉터에 전류미러회로가 접속되고, 차동쌍 트랜지스터중 일측의 베이스에 기준전위회로가 접속되는 한편 다른 측의 베이스에 전류미러회로의 출력전류를 부귀환하는 회로수단이 설치되며, 다른 측의 베이스와 접지사이의 전압이 다링톤접속된 트랜지스터중 입력단 트랜지스터에 바이어스전원으로서 공급되고 있다. 따라서, 다링톤접속된 트랜지스터중 출력단 트랜지스터의 베이스전류에 상당하는 전류에 의해 입력단 트랜지스터를 항상 전류바이어스할 수 있기 때문에 다링톤구성의 증폭단의 본래의 전류이득을 저하시키지 않고 출력단의 바이어스전류를 설정할 수 있으면서 왜곡성분을 감소시키는 것이 가능하다.According to the present invention configured as described above, a current mirror circuit is connected to a collector of a differential pair transistor in which a common emitter is biased by a constant current source, and a reference potential circuit is connected to a base of one side of the differential pair transistor, while the base of the other side is connected. Circuit means for negatively feeding back the output current of the current mirror circuit is provided, and the voltage between the base and the ground of the other side is supplied as a bias power supply to the input terminal transistor among the transistors to which Darlington is connected. Therefore, since the input terminal transistor can always be current biased by the current corresponding to the base current of the output stage transistor among the Darlington connected transistors, the bias current of the output stage can be set without lowering the original current gain of the amplifying stage having the Darlington configuration. It is possible to reduce the distortion component while being present.

(실시예)(Example)

이하, 본 고안의 실시예에 대해 도면을 참조해서 설명한다.Hereinafter, embodiments of the present invention will be described with reference to the drawings.

제1도에서 전원(Vcc)이 공급되는 전원단자(10)에는 기준전압원회로(11)와, 이 기준전압원회로(11)에 의해 바이어스되는 증폭회로(12)가 접속되어 있다.In Fig. 1, the power supply terminal 10 to which the power supply Vcc is supplied is connected to a reference voltage source circuit 11 and an amplifying circuit 12 biased by the reference voltage source circuit 11.

상기 기준전압원회로(11)에서 일단이 상기 전원단자(10)에 접속된 정전류원(13)의 타단은 차동쌍(14)을 구성하는 PNP트랜지스터(Q11, Q12)의 에미터에 접속되어 있고, 상기 트랜지스터(Q11)의 베이스는 다이오드 접속된 트랜지스터(Q15)를 매개해서 접지되어 있으며, 그 콜렉터는 전류미러회로(15)를 구성하는 PNP트랜지스터(Q13)의 콜렉터와 베이스 및 NPN트랜지스터(Q14)의 베이스에 접속되어 있다. 또, 트랜지스터(Q14)의 콜렉터는 상기 트랜지스터(Q12)의 콜렉터와 베이스에 접속되어 있다.The other end of the constant current source 13 whose one end is connected to the power supply terminal 10 in the reference voltage source circuit 11 is connected to the emitters of the PNP transistors Q11 and Q12 constituting the differential pair 14, The base of the transistor Q11 is grounded via a diode-connected transistor Q15, the collector of which is the collector and base of the PNP transistor Q13 constituting the current mirror circuit 15, and the base of the NPN transistor Q14. It is connected to the base. The collector of transistor Q14 is connected to the collector and base of transistor Q12.

상기 트랜지스터(Q12)의 베이스는 저항(Ri)을 매개해서 증폭회로(12)를 구성하는 NPN트랜지스터(Q16)의 베이스에 접속되어 있고, 이 베이스에는 결합용량(Ci)를 매개해서 신호원(Vi)이 접속되어 있으며, 상기 트랜지스터(Q16)는 PNP트랜지스터(Q17)와 역다링톤접속되어 있다.The base of the transistor Q12 is connected to the base of the NPN transistor Q16 constituting the amplifying circuit 12 via a resistor Ri, and the base has a signal source Vi via a coupling capacitance Ci. Is connected, and the transistor Q16 is inversely connected to the PNP transistor Q17.

즉, 트랜지스터(Q16)의 에미터는 접지되어 있고, 그 콜렉터는 트랜지스터(Q17)의 베이스에 접속되어 있다. 또, 이 트랜지스터(Q17)의 에미터는 상기 전원단자(10)에 접속되는 한편, 이 트랜지스터(Q17)는 출력단자(16)에 접속됨과 더불어 저항(R_L)을 매개해서 접지되어 있다.That is, the emitter of the transistor Q16 is grounded, and the collector thereof is connected to the base of the transistor Q17. The emitter of this transistor Q17 is connected to the power supply terminal 10, while the transistor Q17 is connected to the output terminal 16 and grounded via a resistor R _L.

상기한 회로는 1:1 전류미러회로(15)를 구성하는 트랜지스터(Q13)의 출력을 트랜지스터(Q12)의 베이스에 부귀환시켜 전압팔로워를 구성하게 된다.The circuit configures a voltage follower by negatively feeding the output of the transistor Q13 constituting the 1: 1 current mirror circuit 15 to the base of the transistor Q12.

따라서, 정전류원(13)으로부터 출력되는 정전류(Iref)의 1/2전류가 콜렉터에 공급되는 트랜지스터(Q11)의 베이스전류에 의해 바이어스되는 트랜지스터(Q15)의 베이스·에미터간 전압이 트랜지스터(Q12)의 베이스에서 얻어지게 된다.Accordingly, the voltage between the base and emitters of the transistor Q15 biased by the base current of the transistor Q11 supplied with the collector by the half current of the constant current Iref output from the constant current source 13 is the transistor Q12. It is obtained at the base of.

한편, NPN트랜지스터(Q15)와 트랜지스터(Q16)의 에미터의 면적비를 1:n으로 하는 한편 PNP트랜지스터의 전류이득을 βP로 하면, 증폭회로(12)의 출력바이어스전류(Io)는,On the other hand, when the area ratio of the emitters of the NPN transistor Q15 and the transistor Q16 is 1: n and the current gain of the PNP transistor is βP, the output bias current Io of the amplifying circuit 12 is

Io = Iref / 2 × 1 / βP×n×βPIo = Iref / 2 × 1 / βP × n × βP

= Iref·n/2= Iref n / 2

로 표시할 수 있다. 증폭회로(12)의 PNP트랜지스터의(Q17)와 기준전압원회로(11)의 PNP트랜지스터(Q11, Q12)는 전류이득이 같다는 조건이 필요하기 때문에 이들 트랜지스터의 에미터면적비도 1:n으로 하는 것이 바람직하게 된다.Can be displayed as Since the PNP transistors Q17 of the amplifying circuit 12 and the PNP transistors Q11 and Q12 of the reference voltage source circuit 11 need to have the same current gain, the emitter area ratio of these transistors should be 1: n. It becomes preferable.

상기 실시예에 따르면, 기준전압원회로(11)에서 차동쌍을 구성하는 PNP트랜지스터(Q11, Q12)의 콜렉터에 NPN트랜지스터(Q13, Q14)에 의해 구성된 전류미러회로가 접속되고, 이 전류미러회로(15)의 출력이 트랜지스터(Q12)의 베이스에 부귀환되도록 함으로써 전압팔로워를 구성하게 된다. 또, 트랜지스터(Q11)의 베이스에 다이오드접속된 트랜지스터(Q15)가 접속되고, 이 트랜지스터(Q15)가 트랜지스터(Q11)의 베이스 전류에 의해 전류바이어스되며, 이 트랜지스터(Q15)의 베이스·에미터간의 전압이 전압팔로워를 매개하여 증폭회로(12)의 트랜지스터(Q16)의 베이스에 공급되고 있다. 따라서, 트랜지스터(Q16, Q17)의 상호간에 종래와 같이 전류미러회로를 구성하는 트랜지스터가 개재되지 않기 때문에 다링톤구성으로서의 전류이득을 얻을 수 있게 된다.According to the above embodiment, the current mirror circuit constituted by the NPN transistors Q13 and Q14 is connected to the collectors of the PNP transistors Q11 and Q12 constituting the differential pair in the reference voltage source circuit 11, and the current mirror circuit ( The output of 15) is negative feedback to the base of the transistor Q12 to configure the voltage follower. In addition, a diode-connected transistor Q15 is connected to the base of the transistor Q11, and this transistor Q15 is current-biased by the base current of the transistor Q11, and between the base and the emitter of this transistor Q15. The voltage is supplied to the base of the transistor Q16 of the amplifier circuit 12 via the voltage follower. Therefore, since the transistors constituting the current mirror circuit are not interposed between the transistors Q16 and Q17 as in the prior art, the current gain in the Darlington configuration can be obtained.

또, 상기 구성에 따르면, 다링톤접속된 트랜지스터(Q16, Q17)의 상호간에 종래와 같이 트랜지스터(Q16)에 흐르는 특정의 전류까지는 트랜지스터(Q17)가 응답하지 않도록 하기 위한 저항이 개재되지 않기 때문에 트랜지스터(Q16)의 변화전류에 대해 트랜지스터(Q17)는 그 트랜지스터가 가지는 전류이득에 의해 응답하게 된다. 따라서 트랜지스터(Q16, Q17) 사이의 관계가 선형(線形)으로 되므로 왜곡성분을 감소시킬 수 있다.In addition, according to the above structure, since the transistor for preventing the transistor Q17 from responding to a specific current flowing through the transistor Q16 does not intervene between the transistors Q16 and Q17 connected to each other, as in the prior art, the transistor The transistor Q17 responds to the change current of Q16 by the current gain of the transistor. Therefore, since the relationship between the transistors Q16 and Q17 becomes linear, the distortion component can be reduced.

제2도는 본 고안의 제2실시예를 나타낸 도면으로, 본 고안을 B급 증폭기에 적용한 예이다. 즉, 본 실시예는 도전성이 다른 트랜지스터에 의해 구성된 제1 및 제2기준전압원회로(11, 11a)와, 도전성이 다른 트랜지스터에 의해 역다링톤회로가 구성된 제1 및 제2증폭회로(12, 12a)를 2개 조합한 것으로, 출력단자(16)에는 콘덴서(Co)와 부하저항(R_L)이 접속되어 있다.2 is a view showing a second embodiment of the present invention, an example of applying the present invention to a class B amplifier. That is, in the present embodiment, the first and second reference voltage source circuits 11 and 11a constituted by transistors having different conductivity and the first and second amplification circuits 12 and 12a constituted by the reverse darling tone circuit are constituted by transistors having different conductivity. ) Is a combination of two capacitors. A capacitor Co and a load resistor R _L are connected to the output terminal 16.

또, 이 제2도에서 제1도와 동일한 부분에는 동일한 참조부호가 부여되어 있고, 제2기준전압원회로(11a)와 제2증폭회로(12a)에 있어서 제1기준전압원회로(11)와 제1증폭회로(12)에 대응하는 부분에는 동일한 부호로 a를 부여해서 표시하고 있다.In FIG. 2, the same reference numerals are given to the same parts as those in FIG. 1, and the first reference voltage source circuit 11 and the first reference voltage source circuit 11a and the second amplifier circuit 12a are denoted by the same reference numerals. In the part corresponding to the amplifier circuit 12, a is denoted by the same reference numeral.

이와 같이 B급증폭기를 구성하는 경우에는 비교적 저전압까지 동작하는 것이 가능하게 되고, 또 이상적(理想的)인 전류(출력단 바이어스전류)의 변동이 작은 증폭기를 제공할 수 있다.In the case of configuring a Class B amplifier in this manner, it is possible to operate to a relatively low voltage, and an amplifier with a small variation in an ideal current (output stage bias current) can be provided.

그리고, 본 고안은 상기 실시예로 한정되지 않고, 그 요지를 변화시키지 않는 범위에서 여러가지로 변형실시 가능함은 물론이다.In addition, this invention is not limited to the said Example, Of course, various deformation | transformation is possible in the range which does not change the summary.

한편, 본원 청구범위의 각 구성요소에 병기한 도면참조부호는 본원 고안의 이해를 용이하게 하기 위한 것으로, 본원 고안의 기술적 범위를 도면에 도시한 실시예로 한정할 의도로 병기한 것은 아니다.On the other hand, the reference numerals written in each component of the claims of the present application to facilitate the understanding of the present invention, not intended to limit the technical scope of the present invention to the embodiments shown in the drawings.

[고안의 효과][Effect of design]

이상에서 설명한 바와 같이 본 고안에 의하면, 높은 전류이득을 가지게 됨과 더불어 왜곡성분이 감소된 다링톤접속의 전류증폭단을 바이어스하는 것이 가능한 기준전압원회로를 제공할 수 있다.As described above, according to the present invention, it is possible to provide a reference voltage source circuit capable of biasing the current amplifier stage of the Darlington connection, which has a high current gain and a reduced distortion component.

Claims

For supplying a bias current to the reverse Darlington circuit comprising a first transistor (Q17) of the first conductivity type having a collector connected to the output terminal and a second transistor (Q16) of the second conductivity type, the input signal of which is supplied to the base. The reference voltage source circuit

The third and fourth transistors Q11 and Q12 of the first conductivity type, each having a base, a collector, and an emitter biased by a constant current, wherein the second transistor Q16 includes the second and the second transistors. A differential amplifier 14 having an emitter region that is an integer multiple of each emitter region of the four transistors Q11 and Q12,

A reference potential circuit Q15 connected to the base of the third transistor Q11 to generate a reference potential,

The fourth and the second according to the reference potential generated by the reference potential circuit Q15, respectively, having a base, a collector connected to the collectors of the second and fourth transistors Q11 and Q12, respectively, and an emitter. And a current mirror circuit (15) comprising the fifth and sixth transistors (Q13, Q14) of the second conductive type to control the base of the transistors (Q12, Q16).

A differential amplifier 14 comprising a third and fourth transistors Q11 and Q12 of the first conductivity type, each having a base, a collector, and an emitter biased by a constant current;

A diode-connected transistor connected to the base of the third transistor Q11 and having an emitter region to generate a reference potential,

A reference potential circuit Q15 having an emitter region in which the first transistor Q17 has an integer multiple of the emitter region of the diode-connected transistor, and

The fourth and the second according to the reference potential generated by the reference potential circuit Q15, each having a base, a collector connected to the collectors of the third and fourth transistors Q11 and Q12, and an emitter, respectively. And a current mirror circuit (15) comprising the fifth and sixth transistors (Q13, Q14) of the second conductive type to control the base of the transistors (Q12, Q16).

A reference voltage source circuit for supplying a bias current to a Darlington circuit comprising a first transistor to which an input signal is supplied to the base and a second transistor having a collector connected to the output terminal,

A differential amplifier comprising a third base and a fourth transistor of each of the first conductive type having a base, a collector, and an emitter;

A constant current source connected to the emitters of the third and fourth transistors for biasing the third and fourth transistors, a reference potential circuit connected to the base of the third transistor to generate a reference potential,

And fifth and sixth transistors each having a base, an emitter, and a collector, wherein the collector and base of the fifth transistor are connected to the collector of the third transistor, and the collector of the fifth transistor is connected to the fourth transistor. A current mirror circuit connected to a collector and a base of the emitter and grounded to emitters of the fifth and sixth transistors;

And resistance means Ri connected between the base of the fourth transistor and the first transistor to supply a voltage serving as a reference bias between the base of the fourth transistor and the ground potential of the base of the first transistor. Reference voltage source circuit, characterized in that.

4. The reference voltage source circuit according to claim 3, wherein the emitter region of the second transistor is an integer multiple of each emitter region of the third and fourth transistors.

4. The reference voltage source circuit according to claim 3, wherein the reference potential circuit includes a seventh diode connected transistor, and the emitter region of the first transistor is an integer multiple of the emitter region of the seventh transistor.

A first darlington circuit comprising a first transistor of a first conductivity type having a base for receiving a first input signal and a second transistor of a second conductivity type having a collector connected to an output terminal, and receiving a second input signal; A reference voltage source circuit for supplying a bias voltage to a second Darlington circuit comprising a third transistor of the second conductive type having a base and a fourth transistor of the first conductive type having a collector connected to the output terminal,

A differential amplifier comprising a base and a fifth and sixth transistor of a second conductivity type having an emitter biased by a first constant current and a collector,

A first reference potential circuit coupled to the base of the fifth transistor by generating a first reference potential.

A seventh and eighth transistors of a first conductivity type with an emitter and a collector connected to a collector of the fifth and sixth transistors, respectively, and the eighth transistor is supplied to the base of the sixth transistor. A current mirror circuit having an output current of

First resistance means for supplying a voltage serving as a reference bias between the base of the sixth transistor and the first potential with respect to the base of the first transistor;

A differential amplifier comprising a base, a collector biased by a second constant current, and a ninth and tenth transistor of a first conductivity type with an emitter,

A second reference potential circuit connected to the base of the ninth transistor to generate a second reference potential;

Respectively comprising a base, connected collectors of collectors of the ninth and tenth transistors, and eleventh and twelfth transistors of a second conductivity type with emitters, wherein the twelfth transistor is supplied to the base of the tenth transistor; A current mirror circuit having an output current,

And second resistance means for supplying a voltage serving as a reference bias between the base of the tenth transistor and the second potential with respect to the base of the third transistor.