KR960006281A

KR960006281A - Address buffer circuit of semiconductor device

Info

Publication number: KR960006281A
Application number: KR1019940016968A
Authority: KR
Inventors: 권정태
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1994-07-14
Filing date: 1994-07-14
Publication date: 1996-02-23
Also published as: KR970004061B1

Abstract

본 발명은 반도체 소자의 어드레스 비퍼에 관한 것으로 어드레스 입력 전압이 전원전압(Vcc)에 가까와지면 입력단의 커런트 소오스(Source) 역할을 하는 PMOS의 전도율이 줄어들고, 이와 반대로 어드레스 입력 전압이 집지 전압(Vss)에 가까와지면 키런트 싱크(Sink) 역할을 하는 NMOS의 전도율이 줄어들고, 또 어드레스 입력이 CMOS 레벨인 경우에는 입력단에서 정적 전류(static current)가 흐르지 않도록 함으로써, 어드레스 버퍼에서의 파워(power) 소비를 감소시킨 어드레스 버퍼 회로에 관한 것이다.The present invention relates to an address beeper of a semiconductor device, and when the address input voltage approaches the power supply voltage (Vcc), the conductivity of the PMOS serving as a current source of the input terminal is reduced, on the contrary, the address input voltage is the holding voltage (Vss). Approaching the NMOS reduces the conductivity of the NMOS, which acts as a quiescent sink, and prevents static current from flowing through the input stage when the address input is at the CMOS level, thereby reducing power consumption in the address buffer. The address buffer circuit is reduced.

Description

Address buffer circuit of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 의한 어드레스 버퍼의 제1실시예를 도시한 회로도.2 is a circuit diagram showing a first embodiment of the address buffer according to the present invention.

제3도는 본 발명에 의한 어드레스 버퍼의 제2실시예를 도시한 회로도.3 is a circuit diagram showing a second embodiment of the address buffer according to the present invention;

Claims

In an address buffer circuit composed of a current source, a sense circuit, a current sink, and a latch circuit, a gate of the transistor M1 composed of the one PMOS is provided at an address input, a source is supplied to a power supply voltage (Vcc), and a drain is cross-crossed from a sense circuit. A current source connected to a source of a cross-coupled PMOS, two NMOS transistors M4 and M5 sharing the source with each other, and a current coupled coupler to amplify a small sensed voltage difference. It consists of a sense circuit composed of two PMOS transistors (M2, M3) connected, and two NMOS transistors (M6, M7) connected in series with each other. The gate of the NMOS transistor M6 is at an address input, and the source is NMOS. The drain of the transistor M7 is connected to a common source of an input level sense circuit, and the gate of the NMOS transistor M7 is a control signal. Or an address buffer circuit comprising a current sink connected to an output of an inverter having the control signal as an input, a source connected to a ground voltage Vss, and a drain connected to a source of an NMOS transistor M6. .

An address buffer circuit comprising a sense circuit, a current sink, and a latch circuit, comprising: two NMOS transistors M10 and M11 sharing the source and two PMOS transistors M8 and M9 having gates connected to address inputs; And a NMOS transistor (M12, M13) connected in series with each other, the gate of the NMOS transistor M12 being the address input, the source being the drain of the NMOS transistor M13, and the drain being the sense circuit. Is connected to the common source of NMOS transistor M13, the gate of the NMOS transistor M13 is connected to the control signal or to the output of the inverter that takes this control signal as input, the source to ground voltage (Vss), and the drain to the source of NMOS transistor M12. And a current sink to be included.

※ Note: The disclosure is based on the initial application.