KR960005389B1 - Input-data memory unit for pc - Google Patents

Abstract

The method is for providing the comfortableness of using the device as a back up when damaged. The unit includes: a storage means(30) for storing the input data from a keyboard; a binary counter(22,24) for generating address signal about the storage means; a bidirectional buffer(18) forming the path which outputs storage data and transmits the input data; a first programmable array logic(14) which provides clock signal(COUNTER CLOCK) for increasing the address signal of the binary counter, record enable signal(SRAM WRITE) which enables recording of input information, reading enable signal(SRAM READ) which enables reading the stored information and data transferring direction control signal(DIRECTION) to the bidirectional buffer(18).

Description

Keyboard input data storage on a personal computer

Is a detailed circuit diagram of a keyboard input data storage device constructed in accordance with the present invention.

* Explanation of symbols for main parts of the drawings

5: password setting switch

12, 14: 1 and 2 programmable array logic 18: bidirectional buffer

22, 24: binary counter 30: SRAM

40: battery backup device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a personal computer (hereinafter referred to as a PC), and more particularly, to an apparatus for storing information input from a keyboard of a personal computer for a period of time.

The information input from the PC through the keyboard is passed to the keyboard controller via the keyboard line, and when the keyboard controller makes an interrupt request to the system, the CPU receives the input value through the BIOS's keyboard controller processing routine. This is handled by reading. In the BIOS keyboard processing routine, there is a ring buffer of a certain size to temporarily store the input key value, and the previously input key value disappears as soon as it is subsequently overwritten depending on the size of the ring buffer.

Today, computer crime is increasing as the use of computers increases, sneaking out information stored on other computers, or in the case of banks, withdrawing money after making a false payment without actually making a deposit. Problems such as thinness have been caused. In particular, it may be necessary to ensure that the confidentiality of a particular company is not leaked to other competitors, and on the other hand, it may be necessary to know what information is being leaked.

Accordingly, the present invention has been made in accordance with the above-described needs, and the information inputted from the personal computer on the keyboard is recorded on a daily basis or a weekly basis so that the contents of the specific computer can be grasped while the user is absent. Its purpose is to provide a convenience that can be used for backup when the contents that have been inputted for a long time or the contents that have been input for a long time are suddenly turned off.

Another object of the present invention is to provide a function that allows the CPU to read the scan code value from the keyboard controller and simultaneously store the data in a separate memory for inquiry as needed.

Hereinafter, the present invention will be described in detail as follows with reference to the accompanying drawings.

Referring to FIG. 1, a key input data storage device constructed in accordance with the present invention is shown as a block diagram. The key input storage device 100 according to the present invention includes storage means 30 for storing input information from a keyboard, and 4-bit binary counters 22 and 24 for supplying an address signal to the storage means 30. And a bidirectional buffer 18 which forms a path for transferring data to the storage means 30 internally and externally, the clock input signal of the binary counters 22 and 24, and the reading of the storage device 30 (READ). Back up the data stored in the storage means 30 and the programmable array logic 12 and 14 forming the write enable signal, the direction control signal of the bidirectional buffer 18, and even when the power is turned off. And a backup circuit 40 for that.

The memory means 30 is composed of an SRAM capable of storing information input through the ISA slot 10 from the keyboard. Data to the SRAM 30 is input through the bidirectional buffer 18. This bidirectional buffer 18 controls the data input to the SRAM 30 and the data output to the outside by the direction control signal.

The first and second binary counters 22 and 24 are connected to the address terminals A0 to A7 of the SRAM 30, respectively, and when a clock signal is provided to the clock terminal CLK thereof, Store the upper address. The second binary counter 24 connected to the upper address terminals A8 to A15 of the SRAM 30 receives a clock signal from the first binary counter 22 to designate a lower address of the SRAM 30.

The 4-pin select switch 5 acts as a password setting switch for a party user, and generates 4-bit binary data by a combination of internal switch contacts. The 4-bit data generated in this way is used as a cipher data value of a party user and is provided to the input terminals P0 to P3 of the first programmable array logic 12.

The first programmable array logic 12 includes an address signal from the address bus AD extending from the ISA slot 10 of the PC, a read signal through the read line IORD of the input / output port, and a write line of the input / output port. Receive a write signal via (IOWR). These signals are provided from the central processing unit (CPU) of the computer system when there is a key input, as described above. The first programmable array logic 12 determines whether the encrypted data set by the setting switch 5 and a part of the address value of the input / output port designated by the CPU, that is, the SRAM 30, are the same. If the two values are the same, the clock signal SRAM ACCESS ON is provided to the clock terminal CLK of the latch 16 of the next stage. This clock signal is a signal that makes the SRAM 30 usable. Compared with the value set by the setting switch 5 and a part of the address signal, this value becomes high when the input address value matches. It is used as a clock signal of the latch 16. However, if an unauthorized person enters or the password is incorrect, the clear signal SRAM ACCESS OFF is output to the clear terminal CLEAR of the latch 16. When this signal is used as the clear signal of the latch 16 in a low state, the output of the latch 16 is brought into a low state by this clear signal, and the signal is used as an access prohibition signal for the SRAM 30.

The latch circuit 16 is configured as a D-type flip-flop and operates according to a clock signal from the first programmable array logic 12 to provide an enable signal to the second programmable array logic 14. This latch circuit 16, together with the first programmable array logic 12, acts as a user source setting means for the RAM 30.

The second programmable array logic 14 receives an address signal and a write signal through the address bus AD extending from the ISA slot 10 of the PC, the read line IORD of the input / output port, and the write line IOWR of the input / output port. And receive a read signal. The second programmable array logic 14 is clocked to the clock terminal CLK of the first binary counter 22 as its output when an enable signal indicating the access function of the SRAM 30 is provided from the latch circuit 16. (COUNTER CLOCK), the readout signal (SRAM READ) and the write signal (SRAM WRITE) to the RD jar and the WR terminal of the SRAM 30, and the reset terminals of the first and second biasing counters 22 and 24. Provide a reset signal (COUNTER RESET) with (RESET).

The reset signal (COUNTER RESET) is used as a clear signal of the counter, and outputs a low state when writing arbitrary data to a newly set input / output port. In particular, the reset signal is used to newly start a read or write operation to the SRAM 30. The clock signal COUNTER CLOCK becomes active when a readout signal for a keyboard input / output port for reading data of a keyboard controller is displayed in a system. This signal is used as a clock input of the counter by being used as a signal for making an address for the SRAM 30. The write signal SRAM WRITE is the same as the counter clock signal COUNTER CLOCK. When the read signal for the keyboard input / output port for reading data of the keyboard controller is displayed in the system, the signal becomes active. This signal is used as a recording signal for the SRAM 30 so that input from the keyboard can be written to the SRAM 30.

The read signal SRAM READ is used as a read signal for the SRAM 30 designated by the CPU when the output of the latch 16 is high. This signal is also provided to the direction control terminal DIR of the bidirectional buffer 18 so that the read signal SRAM READ from the first PAL 12 is used to indicate the direction of data input / output of the buffer 18. DIRECTIOW). When the read signal SRAM READ is active, the signal direction of the bidirectional buffer 18 is determined from the outside to the SRAM 30.

In addition, the present invention further includes a backup circuit 40 by a battery for storing information in the SRAM 30 even when the personal computer is turned off. The backup circuit 40 is configured to supply the computer power to the SRAM 30 through the transistors Q1 and Q2 while the volt computer is turned on using the rechargeable battery BAT. When turned off, power from the battery BAT is supplied via the diode D2. The role of the diode D1 and the resistor R1 is to perform a charging function for the rechargeable battery BAT when the power is turned on.

The operation of the key input data storage device having the above configuration is explained as follows.

When the power is reset to the SRAM 30, the clear terminals of the counters 22 and 24, which generate the address of the SRAM 30 for storing the input of the keyboard, are in a low state, and the outputs of the counter are both set to '0000'. Keep it. Then, when the CPU reads the keyed scan code from the keyboard, i.e., when the keyboard controller is in the read state, the SRAM 30 according to the present invention writes the key value to the SRAM 30 on the data line at that moment. That is, the read signal for the keyboard controller is used as the write signal for the SRAM 30. The continuously read value for the keyboard controller is continuously written to the SRAM 30. Input scan code values from the keyboard are stored in the SRAM 30 as described below. When the power is turned off, the information stored in the SRAM 30 is powered by the battery backup circuit 40, and thus the power off state. In addition, the previously input kisscan code value can be assisted.

The SRAM write enable signal SRAM WRITE is generated at the output of the programmable array logic 14 the moment a data is read from the keyboard controller, i. The clock signal COUNTER CLOCK is input to the clock terminals CLK of the counters 22 and 24. Thus, the outputs of the binary counters 22 and 24 are incremented by one each time a keyboard controller readout signal from '0000H' is provided to the (IOWR) line of the ISA slot 10. The contents of the keyboard scan code provided to the data line in the keyboard controller are loaded onto the data line of the SRAM 30 via the bidirectional buffer 18 and when the read signal of the keyboard controller appears, the output of the programmable array logic 14 is Since the line becomes active and the line is connected to the write terminal WR of the SRAM 30, when the read signal to the keyboard controller indicates, the information (keyboard scan code) carried on the data line is displayed in the SRAM 30. Is written on. Thereafter, whenever there is a keyboard input, the CPU reads the keyboard scan code from the keyboard controller and at the same time the data is stored in the SRAM 30 of the present invention. Assuming that the key input speed of an experienced person is 5 to 7 strokes per second, assuming 10 hours of use per day, it is possible to input about 36,000 × 10 × 5 = 180,000, and if the amount of information is enough, 64K SRAM 30 Dogs are possible. If necessary, increasing the capacity of the SRAM 30 can store all inputs for a longer period (one week or longer).

After the input of the necessary period or when the inquiry of the stored input data is necessary, the contents of the SRAM 30 can be read out by the read signal of the newly expanded input / output port.

First, the read or write operation of the extended input / output port is preceded to generate an active low signal at the clear terminals of the binary counters 22 and 24 (in this case, the binary counter outputs all zeros, and then the binary counter. Each time the clock inputs of 22 and 24 come in, the output of the counter is increased by one, and the clock inputs of the binary counters 22 and 24 are connected to the read control signal of the SRAM 30 to the SRAM 30. The stored contents can be read from the CPU via the bidirectional bus 18. The read signal is connected to the VCC terminal or converted to the outputs of the PALs 12 and 14 as a defense against reading the contents of the SRAM 30. You can also use the selector switch to connect it.

In addition, by operation of the battery backup circuit 40, what kind of information is performed on information of what contents even if the power is turned off after being used without permission in order to eliminate the trace of the use of the personal computer other than the proper user. By backing up the contents of the SRAM to a battery, you can turn it back on and read it.

According to the present invention described above, if the input data is lost due to a sudden power outage and the key input data is quickly lost due to duplicate recording of new input data, it may be lost due to a sudden power failure or the like. It can prevent leakage and can be useful for this purpose.

Claims (6)

Storage means 30 for storing input data from the keyboard; Binary counters 22 and 24 for generating an address signal for said storage means 30; A bidirectional buffer 18 for transmitting said input data to said storage means 30 and forming a path for outputting stored data; A clock signal for increasing the address signals of the binary counters 22 and 24, a write enable signal SRAM WRITE that enables the input information to be written to the storage device 30, and stored information. Keyboard input data storage device of a personal computer including a read enable signal (SRAM READ) to enable reading and a first programmable array logic (14) for providing a data transfer direction control signal (DIRECTION) to the bidirectional buffer (18). . A switching means (5) for setting a password of a political party user; Means (16) for providing an enable signal to said programmable array logic (14); The data indicating the password set by the selection switch 5 and a part of the address AD signal provided from the control means CPU of the personal computer are compared to the programmable array logic 14 for the storage means 30. And license setting means (12 and 16) for providing a license signal or a ban signal indicating an accessible or inaccessible signal to the personal computer. 3. The license setting means according to claim 2, wherein the license setting means provides an operation clock signal (SRAM ACCESS ON) indicating a permission signal for the storage means (30) when the comparison result matches and when the comparison result does not match. A second programmable array logic (12) for providing said latch circuit (16) with a clear signal (SRAM ACCESS OFF) indicative of an access prohibition signal for said storage means (30); A latch circuit 16 for outputting a corresponding enable and disable signal to the first programmable array logic 14 in response to the clock signal and the clear signal of the second programmable array logic 12, respectively; Keyboard input data storage device of a personal computer provided. 4. The first programmable array logic (14) of claim 3, wherein the first programmable array logic (14) generates a reset signal (COUNTER RESET) for prohibiting the count operation of the binary counters (22 and 24) in accordance with a prohibition signal provided from the latch circuit (16). Keyboard input data storage device of the personal computer to output. 2. The keyboard input data storage device according to claim 1, further comprising a battery backup means (40) for providing a backup power source in order to prevent loss of information in said storage means (30) when the power supply is turned off. The keyboard input data of the personal computer according to claim 1, wherein the data transfer direction control signal DIRECTION provided from the fraud first programmable array logic 14 to the bidirectional buffer 18 is the same as the write enable signal SRAM WRITE. Storage device.