KR960003753B1 - Etching method of gate poly-silicon film - Google Patents
Etching method of gate poly-silicon film Download PDFInfo
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- KR960003753B1 KR960003753B1 KR1019920027303A KR920027303A KR960003753B1 KR 960003753 B1 KR960003753 B1 KR 960003753B1 KR 1019920027303 A KR1019920027303 A KR 1019920027303A KR 920027303 A KR920027303 A KR 920027303A KR 960003753 B1 KR960003753 B1 KR 960003753B1
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- etching
- polysilicon film
- gate
- gate oxide
- film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Abstract
Description
본 발명은 64M DRAM 이상의 고집적 반도체소자의 제조 공정에 관한 것으로, 특히 게이트 폴리실리콘막의 식각방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fabrication process of a highly integrated semiconductor device of 64M DRAM or more, and more particularly, to an etching method of a gate polysilicon film.
일반적으로, 마이크로파를 이용한 ECR(Eletron Cyclotron Resonance ; 이하 ECR이라 칭함) 식각장비에서 게이트 폴리실리콘막을 에칭하는 경우, 종래의 기술에서는 1단계 공정 또는 2단계 공정방법을 사용하여 진행하였다.In general, in the case of etching the gate polysilicon film in an ECR (Eletron Cyclotron Resonance) etching equipment using microwave, in the prior art, a one-step process or a two-step process method was performed.
상기 1단계 공정은, 한가지 공정조건으로 주식각 및 과도식각 공정을 동시에 진행하는 방법이고, 2단계 공정은 주식각 공정과 과도식각 공정을 공정조건이 서로 다른 두 공정 조건하에서 행하는 방법을 먼저 주 공정을 진행하고, 공정의 균일도를 위해 잔류 물질을 제거 하기 위한 과도식각을 하게 된다. 이 과도식각은 게이트 산화막의 손상을 방지하기 위해서 게이트 산화막과의 선택도가 매우 높은 공정조건을 사용하여 식각을 진행하는 방법이다.The first step is a process of simultaneously performing the stock etch and the transient etching process under one process condition, and the second step is the process of performing the stock angular process and the transient etching process under two different process conditions. Proceed with over-etching to remove residual material for uniformity of the process. This transient etching is a method of etching using a process condition having a very high selectivity with the gate oxide film in order to prevent damage to the gate oxide film.
따라서 기존 공정에서는 RF(Radio Frequence ; 이하 RF라 칭함)전원, 압력, 가스량등의 공정조건을 변화시켜 산화막과의 선택도를 높이는 방법을 사용하여 왔다.Therefore, in the existing process, a method of increasing selectivity with an oxide film has been used by changing process conditions such as RF (Radio Frequence) power, pressure, and gas amount.
그러나 기존 ECR 장비에서 식각속도, 식가형태, 선택도 등을 고려할 때, 1단계 공정을 사용하는 경우 게이트 산화막과의 선택도가 낮아(20 내지 30 : 1) 64M DRAM 이상의 고집적 소자와 같이 게이트 산화막의 두께가 작은 경우 게이트 산화막에 손상을 줄 문제가 있으며, 2단계 공정을 사용하는 경우는 하드웨어(Hardware)상의 제약, 즉 주식각과 과도식각의 공정조건이 매우 다른 경우 장비가 불안정하게 되어 공정특성이 저하되는 단점 때문에 공정변수의 변화폭이 작아져 선택도를 향상시키는데 한계점에 도달하게 되는 문제점이 있었다.However, considering the etch rate, food type, selectivity, etc. in the existing ECR equipment, when the one-step process is used, the selectivity with the gate oxide is low (20 to 30: 1). If the thickness is small, there is a problem of damaging the gate oxide.In case of using the two-stage process, the hardware becomes unstable when the process conditions of stock angle and transient etching are very different. Due to the drawbacks, there is a problem that the limit of change in the process variable is reached and the selectivity is improved.
또한 현재 ECR 식각장비에서는 동일한 공정조건에서 RF 전원의 변화, 가스량변화, 압력의 변화등 제한적인 변화를 통해서 선택도를 높이거나, 저온식각에 의한 선택도 증가 방법을 사용하고 있다. 이 방법 역시 공정변수의 제한적인 변화를 통해서는 선택도의 대폭적인 증가를 기대하기 어렵고, 저온공정을 사용하는 경우는 냉각장치등을 사용하여야 하는 등의 하드웨어상의 문제점이 많았다.In addition, current ECR etching equipment uses a method of increasing selectivity through limited changes such as RF power change, gas volume change, and pressure change under the same process conditions, or using a method of increasing selectivity by low temperature etching. In this method, too, it is difficult to expect a significant increase in selectivity through limited changes in process variables. In low temperature processes, there are many hardware problems such as the use of a cooling device.
따라서, 상기 문제점을 해결하기 위하여 안출된 본 발명은 게이트 산화막의 손상 없이 높은 선택도를 가지는 게이트 폴리실리콘막 식각 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a gate polysilicon film etching method having high selectivity without damaging the gate oxide film.
상기 목적을 달성하기 위하여 본 발명은, 마이크로파를 이용한 ECR(Eletron Cylotron Resonance) 식각장비에서 게이트 폴리실리콘막 식각하는 제 1단계 및 상기 제 1 단계 후에 RF전원을 인가하지 않은 상태에서 다운스트림(Downstraem)에 의한 레디컬(Radical)의 화학적인 반응을 이용하여 잔류 폴리실리콘막을 식각하는 제 2 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a first step of etching a gate polysilicon film in an ECR (Eletron Cylotron Resonance) etching apparatus using microwaves and a downstream (Downstraem) without applying RF power after the first step. And a second step of etching the residual polysilicon film by using a radical chemical reaction.
이하, 본 발명의 일실시예를 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail.
본 발명은 주식각공정을 진행한 후에, 장비의 균일성 및 웨이퍼 상의 공정조건에 의해서 발생하는 잔류물질을 제거하기 위한 과도식각 공정에서 RF전원을 인가하지 않아 이온의 영향을 배제하고, 다운스트림(Downstraem)의 의한 레디컬(Radical)의 화학적인 반응을 이용하여 균일도를 위한 식각을 행하는 방법으로 폴리실리콘막과 게이트 산화막과의 선택도가 100 : 1 이상인 고선택도 폴리실리콘막 식각을 행하는 방법이다.The present invention does not apply the RF power in the transient etching process to remove the residual material generated by the uniformity of the equipment and the processing conditions on the wafer after the stock angle process, to exclude the influence of ions, It is a method of etching for uniformity by using radical chemical reaction by Downstraem. It is a method of etching high selectivity polysilicon film with selectivity of 100: 1 or more between polysilicon film and gate oxide film. .
그리고 상기 게이트 폴리실리콘막의 식각 조건은 표1과 같다.The etching conditions of the gate polysilicon film are shown in Table 1.
[표 1] 게이트 폴리실리콘막의 식각 조건[Table 1] Etch Conditions of Gate Polysilicon Film
상기와 같이 이루어지는 본 발명은 게이트 폴리실리콘막 식각시 게이트 산화막의 손상을 방지하여 게이트 산화막의 신뢰성을 향상시키며, 따라서 64M DRAM 이상의 고집적 반도체 소자에서와 같이 게이트 산화막의 두께가 작은 경우 식각에 의한 손상을 방지하여 소자의 신뢰성을 향상시킬 수 있는 효과가 있다.As described above, the present invention improves the reliability of the gate oxide layer by preventing damage to the gate oxide layer during etching of the gate polysilicon layer. Therefore, when the gate oxide layer is small in thickness, such as in a highly integrated semiconductor device of 64M DRAM or more, the damage caused by etching is prevented. There is an effect to improve the reliability of the device by preventing.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920027303A KR960003753B1 (en) | 1992-12-31 | 1992-12-31 | Etching method of gate poly-silicon film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920027303A KR960003753B1 (en) | 1992-12-31 | 1992-12-31 | Etching method of gate poly-silicon film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940015688A KR940015688A (en) | 1994-07-21 |
| KR960003753B1 true KR960003753B1 (en) | 1996-03-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920027303A KR960003753B1 (en) | 1992-12-31 | 1992-12-31 | Etching method of gate poly-silicon film |
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| KR (1) | KR960003753B1 (en) |
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1992
- 1992-12-31 KR KR1019920027303A patent/KR960003753B1/en not_active IP Right Cessation
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| KR940015688A (en) | 1994-07-21 |
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