KR960003246A - Test unit - Google Patents

Abstract

The present invention is to test the voice and data subscribers using the tester by intensively configuring the connection of various subscriber cards in front of the test unit through the test bus for the circuit separation function and the channel selection test necessary for testing the subscriber line and the call path. It is about the implementation of test units that can be used. In other words, the test connection relay driver, various buffers, various decoders, backup non-volatile racks, etc., have various subscriber connection parts through the test bus to communicate with the end of the line in order to implement the functions of the test unit having the test function and the memory backup function. However, it is possible to select the subscriber who wants to test and perform the test by operating buttons and switches while all the test units are fixed and the tester is fixed.

Description

Test unit

As this is a public information case, the full text was not included.

1 is an overall block diagram of a test unit constructed in accordance with the present invention.

Claims (17)

Test bus, E, M signal line and test connection relay driver for selection of OCU-T, OCU-R line, concentration converter for data line level conversion, address decode, I / O buffer, output buffer, test connection control unit, non-volatile RAM for backing up operation data and performance monitoring data of main control part, test LED indicating that the channel to be tested is currently under test, fault LED indicating unit failure , Test unit machined with indicator. The apparatus of claim 1, wherein the front of the unit test includes a anti-tamper jack into which a tester can be inserted, a switch unit for selecting a channel unit and a channel number, an indicator for displaying a channel unit and a channel number, and a test or use of the corresponding channel. Test LED to inform the user, Fault LED to indicate the fault or abnormal circuit pack status, IN / OUT / NORM 3-stage switch to select the channel and channel of the subscriber channel to be tested. A test unit, characterized by comprising a three-stage AD /. / DA switch for distinguishing input data. The test unit of claim 1, wherein the test bus comprises test patterns T, R, TI, RI, E, M, El, Ml, 8k, C1ock, 64k, and clock. . The test unit according to claim 1, wherein the non-volatile RAM main control unit backs up operation data and performance monitoring data of the main control unit at the time of failure and disengagement, and uploads the current data when the main control unit is restored again. The method of claim 2, wherein the anti-tamper jack is for inserting the tester, the first hole is T, R / DS0-T, the second hole is T1, Rl / DS0-R, the third hole is E / OCU-T, the fourth hole is M / OCU-R is a test unit that uses the 5th hole as 64k clock and the 6th hole as 8k clock. The method of claim 2, wherein the anti-tamper jack is for inserting a test jig, the first hole is the transmission data (+) (-), the second hole is the reception data (+) (-), the third hole for the 67 × N data service test The test unit can be used as the transmission timing (+), the fourth hole is the transmission timing (,-), the fifth hole is the reception timing (+), and the sixth hole is the reception timing (-). The test unit according to claim 5 or 6, wherein the anti-tamper jack is used in two or more modes so that the use can be changed using relay switching. The test unit according to claim 2, wherein the switch for selecting a channel unit and a channel number selects a channel unit from 01 to 99 and a channel number from 1 to 9. Test bus, E.M signal line and test connection relay driver for selection of OCU-T, OCU-R line, concentration converter for data line level conversion, address decoding, I Non-volatile RAM required to back up / O buffer, output buffer, test connection control unit, operation data and performance monitoring data of main control unit, test LED indicating that the channel to be tested is currently in service or under test, and unit failure It consists of fault LED, IN / OUT / NORM 3-stage switch and indicator for selecting the channel and channel of subscriber channel to test, anti-tamper jack, channel unit and channel number to insert tester on the front of the test unit. Switch unit for selecting the channel unit and indicator for displaying the channel number, test LE indicating the test or busy of the corresponding channel D, a test unit, characterized in that the fault LED is configured to indicate a fault or abnormal state of the circuit pack. The method of claim 5. A test unit, characterized in that provided in the IN / OUT / NORM three-stage switch rate switch unit for selecting the line and the channel of the subscriber channel to be tested. The relay operation according to claim 10, wherein the IN / OUT / NORM three-stage switch 12 changes the switch to a test mode other than NORM in a state where the IN / OUT / NORM three-stage switch 12 is once set to TEST IN or TEST OUT. Test unit, characterized in that automatically switched without the operation of the test switch 15 for. 10. The method of claim 9, further comprising: checking whether the test pack is in a normal state through a fault LED, checking whether the test LED is lit, and selecting a line and a call path (IN / OUT / NORM 3-stage switch). Toggle) to the desired side, select channel unit number and channel number by using pushbutton switch, check indicator, and select test channel to activate relay by selected channel and assign according to channel type. The test unit, characterized in that for measuring the desired test item by inserting a tester into the six-hole anti-tamper jack. The test unit according to claim 5, wherein the nonvolatile RAM backs up the operation data and the performance monitoring data of the main control part when the main control part breaks down and loses, and uploads the current data when the main control part returns again. The method of claim 9, wherein the anti-tamper jack is for inserting the tester, the first hole is T, R / DS0-T, the second hole is T1, R1 / DS0-R, the third hole is E / OCU-T, and the fourth hole is M / OCU-R is a test unit that uses the 5th hole as 64k clock and the 6th hole as 8k clock. The test unit according to claim 9, wherein the anti-tamper jack writes the first hole as the transmission mode and the second hole as the reception mode when the analog / analog test function is inserted in the test unit. The test unit according to claim 9, wherein the switch for selecting the channel unit and the channel number can select the channel unit from 01 to 99 and the channel number from 1 to 9. The test unit according to claim 9, wherein the test bus comprises test patterns T.R, TI, RI, E, M, El, Ml, 8k, Clock, 64k, and Clock. ※ Note: The disclosure is based on the initial application.