KR960003122A - Viterbi Decoder - Google Patents

Viterbi Decoder Download PDF

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Publication number
KR960003122A
KR960003122A KR1019940014707A KR19940014707A KR960003122A KR 960003122 A KR960003122 A KR 960003122A KR 1019940014707 A KR1019940014707 A KR 1019940014707A KR 19940014707 A KR19940014707 A KR 19940014707A KR 960003122 A KR960003122 A KR 960003122A
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KR
South Korea
Prior art keywords
phase
input signal
viterbi
value
signal
Prior art date
Application number
KR1019940014707A
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Korean (ko)
Other versions
KR0131547B1 (en
Inventor
심영석
여훈구
Original Assignee
김영욱
생산기술연구원
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Application filed by 김영욱, 생산기술연구원 filed Critical 김영욱
Priority to KR1019940014707A priority Critical patent/KR0131547B1/en
Publication of KR960003122A publication Critical patent/KR960003122A/en
Application granted granted Critical
Publication of KR0131547B1 publication Critical patent/KR0131547B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing

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  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)

Abstract

본 비터비 복호기는 디지탈방식의 송수신시스템에 있어서, 수신부의 비터비 복호화처리시 입력신호를 1차원적인 값으로 대체시켜 기준신호와의 거리를 계산함으로써 입력신호와 기준신호간의 거리계산량을 줄이기 위한 것이다. 이를 위하여 본 장치는 부호화형태의 입력신호가 인가되면, 입력신호에 대응되는 위상신호를 추출하기 위한 위상추출부; 위상추출부에서 출력되는 위상값과 위상값으로 표현되는 소정의 기준값들과 위상차이를 계산하고, 계산된 위상차이값들과 과거의 신호들간의 연관성을 이용하여 최적값으로 판정된 위상을 갖는 기준값을 출력하기 위한 비터비 판정부; 비터비 판정부에서 출력되는 위상값에 대응되는 로드로 매핑하여 비터비 복호화결과 데이터로 출력하는 코드매퍼를 포함하도록 구성된다.The Viterbi decoder is for reducing the distance calculation amount between the input signal and the reference signal by calculating the distance between the input signal and the reference signal by replacing the input signal with a one-dimensional value in the Viterbi decoding process of the receiver. . To this end, the present invention comprises a phase extraction unit for extracting a phase signal corresponding to the input signal when the input signal of the encoding type is applied; A reference value having a phase determined as an optimal value is calculated by calculating a phase difference and a predetermined reference value represented by the phase value and the phase value output from the phase extractor, and using the correlation between the calculated phase difference values and the past signals. Viterbi determination unit for outputting; And a code mapper that maps to a load corresponding to the phase value output from the Viterbi determination unit and outputs the Viterbi decoding result data.

Description

비터비 복호기Viterbi Decoder

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 따른 비터비 복호기의 볼럭도,3 is a block diagram of a Viterbi decoder according to the present invention;

제4도는 본 발명에 따른 비터비 판정방법에 대한 흐름도4 is a flowchart of a Viterbi determination method according to the present invention.

Claims (2)

디지탈방식의 송수신시스템에 사용되는 비터비 복호기에 있어서; 부호화형태의 입력신호가 인가되면, 상기 입력신호에 대응되는 위상신호를 추출하기 위한 위상추출부; 상기 위상추출부에서 출력되는 위상값과 위상값으로 표현되는 소정의 기준값들과 위상차이를 계산하고, 계산된 위상차이값들과 과거의 신호들간의 연관성을 이용하여 최적 값으로 판정된 위상을 갖는 기준값을 출력하기 위한 비터비 판정부; 상기 비터비 판정부에서 출력되는 위상값에 대응되는 코드로 매핑하여 비터비 복호화결과 데이터로 출력하는 코드매퍼를 포함함을 특징으로 하는 비터비 복호기.A Viterbi decoder used in a digital transmission / reception system; A phase extraction unit for extracting a phase signal corresponding to the input signal when an input signal of an encoding type is applied; The phase difference outputted from the phase extracting unit and the predetermined reference values represented by the phase value and the phase difference is calculated, and having a phase determined as an optimal value using the correlation between the calculated phase difference values and the past signals. A Viterbi determination unit for outputting a reference value; And a code mapper for mapping the code corresponding to the phase value output from the Viterbi determination unit to output the Viterbi decoding result data. 제1항에 있어서, 상기 위상추출부는 상기 입력신호를 어드레스신호로 하고, 지정된 어드레스에 저장 데이터를 상기 위상신호로 출력하는 룩업테이블로 이루어짐을 특징으로 하는 비터비 복호기.The Viterbi decoder of claim 1, wherein the phase extractor comprises a lookup table that uses the input signal as an address signal and outputs stored data as the phase signal at a designated address. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940014707A 1994-06-25 1994-06-25 Vitervi decoder KR0131547B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940014707A KR0131547B1 (en) 1994-06-25 1994-06-25 Vitervi decoder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940014707A KR0131547B1 (en) 1994-06-25 1994-06-25 Vitervi decoder

Publications (2)

Publication Number Publication Date
KR960003122A true KR960003122A (en) 1996-01-26
KR0131547B1 KR0131547B1 (en) 1998-10-01

Family

ID=19386315

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940014707A KR0131547B1 (en) 1994-06-25 1994-06-25 Vitervi decoder

Country Status (1)

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KR (1) KR0131547B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010081412A (en) * 2000-02-14 2001-08-29 김효근 Branch metric calculator of viterbi decoder only with the demodulated phase in coded mpsk transmission

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010081412A (en) * 2000-02-14 2001-08-29 김효근 Branch metric calculator of viterbi decoder only with the demodulated phase in coded mpsk transmission

Also Published As

Publication number Publication date
KR0131547B1 (en) 1998-10-01

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