KR960002850A - Method of constructing ferroelectric capacitor circuit - Google Patents

Method of constructing ferroelectric capacitor circuit Download PDF

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Publication number
KR960002850A
KR960002850A KR1019940015290A KR19940015290A KR960002850A KR 960002850 A KR960002850 A KR 960002850A KR 1019940015290 A KR1019940015290 A KR 1019940015290A KR 19940015290 A KR19940015290 A KR 19940015290A KR 960002850 A KR960002850 A KR 960002850A
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KR
South Korea
Prior art keywords
capacitor circuit
constructing
ferroelectric capacitor
lower electrode
ferroelectric
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Application number
KR1019940015290A
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Korean (ko)
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KR100282262B1 (en
Inventor
유인경
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김광호
삼성전자 주식회사
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Priority to KR1019940015290A priority Critical patent/KR100282262B1/en
Publication of KR960002850A publication Critical patent/KR960002850A/en
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Publication of KR100282262B1 publication Critical patent/KR100282262B1/en

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  • Semiconductor Memories (AREA)

Abstract

본 발명은 강유전체 캐패시터 회로의 구성방법에 관한 것으로, 좀더 상세하게는 강유전체(1)의 하부에 하부전극(2)을 형성시키고 상기 강유전체(1)의 상부에 단수 또는 복수개의 단수 또는 복수개의 상부전극(3)을 형성시키는 강유전체 캐패시터 회로의 구성방법에 있어서, 상기 하부전극(2)을 그라운딩시키거나, 또는 상부전극(3)과 하부전극(2)을 연결시키므로서 임프린트를 최소화시켜 리텐션 효과를 증대시킬 수 있고 재료개발이나 구조개발로서 한계가 있는 물성특성을 설계로서 극복할 수 있는 FRAM개발을 용이하게할 수 있는 강유전체 캐패시터 회로의 구성방법에 관한 것이다.The present invention relates to a method of constructing a ferroelectric capacitor circuit, and more particularly, to form a lower electrode (2) below the ferroelectric (1) and the singular or plural singular or plural upper electrodes on the ferroelectric (1) (3) In the method of constructing a ferroelectric capacitor circuit, grounding the lower electrode (2) or connecting the upper electrode (3) and the lower electrode (2) to minimize the imprint to minimize the retention effect The present invention relates to a method of constructing a ferroelectric capacitor circuit that can increase the size of the FRAM and facilitate the development of a FRAM capable of overcoming the design properties of materials that are limited in material development or structure development.

Description

강유전체 캐패시터 회로의 구성방법Method of constructing ferroelectric capacitor circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1(마)도는 본 발명의 강유전체 캐패시터 연결회로의 예들을 도시한 단면도이다.1 (e) is a cross-sectional view showing examples of the ferroelectric capacitor connecting circuit of the present invention.

Claims (5)

강유전체(1)의 하부의 하부전극(2)을 형성시키고 상기 강유전체(1)의 상부에 단수 또는 복수개의 상부전극(3)을 형성시키는 강유전체 캐패시터 회로의 구성방법에 있어서, 상기 하부전극(2)을 그라운딩시킨 것을 특징으로 하는 강유전체 캐패시터 회로의 구성방법.In the method of constructing a ferroelectric capacitor circuit in which a lower electrode 2 under the ferroelectric 1 is formed and a single or a plurality of upper electrodes 3 are formed on the ferroelectric 1, the lower electrode 2 Method for constructing a ferroelectric capacitor circuit characterized in that the grounding. 제1항에 있어서, 상기 하부전극(2)에 저항을 연결시킨 것을 특징으로 하는 강유저체 캐패시터 회로의 구성방법.The method of claim 1, wherein a resistance is connected to the lower electrode (2). 강유전체(1)의 하부에 하부전극(2)을 형성시키고 상기 강유전체(1)의 상부에 단수 또는 복수개의 상부전극(3)을 형성시키는 강유전체 캐패시터 회로의 구성방법에 있어서, 상기 상부전극(3)과 하부전극(2)을 연결시킨 것을 특징으로 하는 강유전체 캐패시터 회로의 구성방법.In the method of constructing a ferroelectric capacitor circuit in which a lower electrode 2 is formed below a ferroelectric 1 and a single or a plurality of upper electrodes 3 are formed on the ferroelectric 1, the upper electrode 3 And a lower electrode (2) connected to each other. 제3항에 있어서, 상기 상부전극(3)과 하부전극(2)을 그라운딩시킨 것을 특징으로 하는 강유전체 캐패시터회로의 구성방법.4. A method according to claim 3, wherein the upper electrode (3) and the lower electrode (2) are grounded. 제3항 또는 4항에 있어서, 상기 상부전극(3)과 하부전극(2)에 저항을 삽입한 것을 특징으로 하는 강유전체 캐패시너 회로의 구성방법.5. A method according to claim 3 or 4, wherein a resistor is inserted in the upper electrode (3) and the lower electrode (2). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940015290A 1994-06-29 1994-06-29 Method of constructing ferroelectric capacitor circuit KR100282262B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940015290A KR100282262B1 (en) 1994-06-29 1994-06-29 Method of constructing ferroelectric capacitor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940015290A KR100282262B1 (en) 1994-06-29 1994-06-29 Method of constructing ferroelectric capacitor circuit

Publications (2)

Publication Number Publication Date
KR960002850A true KR960002850A (en) 1996-01-26
KR100282262B1 KR100282262B1 (en) 2001-02-15

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KR1019940015290A KR100282262B1 (en) 1994-06-29 1994-06-29 Method of constructing ferroelectric capacitor circuit

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980027519A (en) * 1996-10-16 1998-07-15 김광호 Ferroelectric Random Accessor Memory with Thermal Charge Discharge Circuit
KR100397603B1 (en) * 1997-01-21 2004-02-11 삼성전자주식회사 Thin film transistor ferroelectric random access memory and manufacturing method thereof

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