KR960001992B1 - Administrative unit-3 signal 1bit leaking sequence circuit of - Google Patents

Abstract

The 1 bit leaking sequence circuit of an administrative unit-3 signal of a synchronous digital hierarchy having an elastic buffer, an overhead clock pulse remover and a bit leaking interval calculating unit comprises a smoothing leaking sequence generator for supplying a request signal of a first bit leaking requesting unit and a signal for adding or removing a pulse to a clock synthesizer, generating a smoothing clock according to an STM-1 clock and supplying it to the elastic buffer.

Description

1-Bit Leaking Sequence Circuit for Management Unit-3 Signals in Synchronous Digital Threshold (SDH)

1 is a conventional circuit diagram

2 is a circuit diagram according to the present invention

3 is an output waveform diagram of the smoothing shaking sequence generator 201 of FIG. 2 according to the present invention.

According to the present invention, the SDH AU-3 signal is generated by generating a 1-bit leaching sequence signal of an administrative unit-3 (AU-3) signal of a synchronous digital hierarchy (SDH) in a broadband transmission system. The present invention relates to a circuit capable of minimizing the influence of jitter by dispersing the Vc-3 signal variation according to the change of the AU-3 point value when converted into a virtual container-3 (VC-3) signal.

In general, the transmission network currently in use consists of three different levels (North America, Europe and Japan) and semi-synchronous transmission equipment that is not sufficiently standardized. This phenomenon makes it difficult to interconnect the world's telecommunications networks and places restrictions on the ability of telephone service providers to choose the equipment of various equipment providers. Synchronous digital hierarchy (SDH) promises to improve this phenomenon.

SDH not only allows communication between countries, but can also be used with similar transmission equipment, and SDH equipment is much more standardized than its pre-synchronized digital hierarchy (PDH) equipment. It is much more efficient to manage and provides a convenient feature to monitor bit error rates from user to other users. In addition, the detailed standardization up to the communication protocol level of the overhead function will not interfere with the efficiency of the function, but will support the intermixing of products from other equipment providers.

Since SDH is derived from the North American SONET standard, it is sometimes confused with Synchro-nous Optical NETwork (SONET).

The concept of SONET was started with North American ranks in mind in the United States. Thus, the initial SONET level was 51.840 Mbps, and the electrical and optical signals were named STS-1 and OC-1, respectively. In contrast, SDH is based on CCITT design G.707, G708, and G.709, 155.520Mbps, which is three times the basic SONET bit rate. This signal is called STM-1 (Synchronous Transport Module Level 1), and its upper layer is called STM-N. The bit rate is the product of 4 ⁴ (N = 1, 2, 3, ...) of the primary layer bit rate.

Virtual containers are designed to allow SDHs to transport different signals characterized by different speeds and structures, without improving the overall network each time a new signal is introduced.

This is obtained by defining a set of sub-signals called virtual boxes (VCs), which are accommodated in the Synchronous Transport Module (STM) and processed at the network nodes independently of their payload.

One VC is composed of a path overhead (POH) and a box (C: container), and the payload therein may be a smaller VC or other signals.

When converting from the SDH AU-3 signal to VC-3, the elastic buffer 105 is used as shown in FIG.

Overhead data is removed while passing through the elastic buffer 105, and only VC-3 data is extracted. If 8-bit data is increased or decreased by a pointer, smoothing is performed by leaking at intervals of 1 bit at a time interval. 3 Data can be obtained.

When (VC-3 + overhead) data is input to the elastic butter 105, only the VC-3 signal is transmitted to the elastic buffer 105 by the generated clock of the overhead clock pulse canceller 101 driven according to the STM clock. When the change of the point occurs, if the signal of 8-bit data is increased or decreased by the signal of the point correcting stage 3 is sent, the time unit to sequentially leak the increased / decreased data by 1 bit unit is set. According to the output of the 1-bit leaking interval calculator 102 and the 1-bit leaking interval calculator 102, a leak request signal is generated in units of 1 bit and input to the clock synthesizer 104.

The clock synthesizer 104 uses a clock of the STM clock stage 2 to add or delete a clock pulse corresponding to one bit of the VC-3 signal by the signal of the one-bit reclaim requester 103. Produce a VC-3 byte capped lead clock. The output of the clock synthesizer 104 generates a smoothed VC-3 clock in the smoothing PLL circuit 90 and is provided to the read clock of the elastic buffer 105. This clock becomes 6.26 MHz so that only the VC-3 signal is present. Extracted.

However, when the analog PLL circuit is used to use the smoothed capped lead clock as described above, there is a problem in that the ASIC is difficult because the circuit configuration becomes complicated and the digitalization cannot be performed.

Accordingly, an object of the present invention is to simplify the configuration to extract the VC-3 signal from the SDH AU-3 signal and to simplify the configuration to minimize the amount of 8-bit increase / decrease data jitter by changing the AU-3 point value. To provide a circuit that can be

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a circuit diagram according to the present invention, which differs from the first diagram in that the smoothing PLL circuit 90 is removed from the configuration, and a smoothing shaking sequence generator at the output of the 1-bit leaching requester 103. A signal for determining the position at which the pulse is to be added or omitted according to its output and provided to the clock synthesizer 104 is added according to the designation of the additional stage 4 in the clock of the STM clock stage 2. It is configured to provide a smoothing lead clock of the elastic buffer 105.

3 is an example of a 1-bit smoothing leaking sequence waveform according to the present invention. Therefore, a specific embodiment of the present invention will be described in detail with reference to FIGS. 2 and 3, when the SDH AU-3 signal is written into the elastic buffer 105, the clock of the STM-1 clock stage 2 is overhead clocked. The overhead of the pulse eliminator 101 is removed so that only the pure VC-3 signal is written to the elastic buffer 105.

The one-bit leaking interval calculator 102 calculates the one-bit leaking time period from the input signal of the pointer change signal stage 3 and provides the one-bit leaking requestor 105 to the one-bit leaking requester 105. 105 generates a 1-bit increment request signal and applies it to the smoothing shaking sequence generator 201.

The smoothing leaking sequence generator 201 generates a 1-bit smoothing leaking sequence signal as shown in FIG. The signal generated by the spring leaching sequence generator 201 is shown in FIG.

The STM signal clock, 155.520 MHz, is divided into three divisions of 51.84 MHz to create a smoothing leaking sequence. The minimum 1-bit leaking interval that can be created in the 1-bit leaching interval 102 is 6 SDH 8 ms frames. Decide The number of pulses of 51.84MHz clock in 6 frames is as follows.

The smoothing leaking sequence is largely divided into 36 cod guns, each consisting of 36 small sections consisting of 30 51.8MHz clock pulses. Each subdivision and subdivision shall be numbered from 1 to 36 as shown in FIG. 3, and only the 36th subdivision shall be "High" in the first Daegu line, and only the 35th and 36th subdivision "High" in the second Daegu line. Make. In this way, the 35th large section makes all the subsections except the first subsection "High", and the 36th Daegu makes all the subsections "High".

If the positive pointer change signal is used, the rising edge of the smoothing shaking sequence is used as a signal that adds (drops) a 1-bit pulse, and conversely, the falling edge is used as a signal that adds (drops) a pulse of 1 bit. Overall, when the smoothing sequence ends and the positive pointer fluctuations, a pulse corresponding to one bit is dropped, and when the negative pointer fluctuations, a pulse corresponding to one bit is added.

The bit leaking interval calculator 102 adjusts the time interval by changing the number of pulses of the small section to 30 x n (n = 1, 2, 3, ...). For example, to adjust the time interval to leak one bit in only 24 frames, the bit leaking interval calculator 103 signals the number of pulses of the small section to be 30 × 4 = 120.

The data input clock of the elastic buffer 105 is a clocked capped 6.264 MHz VC-3 byte at the overhead position, and the output VC-3 lead clock of the elastic buffer 105 is smoothed and equalized. It is a new 6.2624 MHz clock smoothed by sequence generator 201. The VC-3 lead clock is generated using a 51.8 MHz clock, which is a three divided clock of the STM-1 signal clock.

First, in a normal state with no pointer fluctuation, clock synthesizer 104 removes one pulse for every 30 pulses of the 51.84 MHz clock in a small section and divides it into eight minutes to produce a 6.264 MHz clock which is a VC-3 byte read clock.

If a pointer change occurs, the clock synthesizer 104 according to the smoothing winning sequence 201 is generated by the positive-negative point change signal from the point change signal terminal 3. When the pulse elimination signal is recognized, one more pulse is removed from the met subsection, and conversely, when the pulse addition signal is recognized, one pulse that has been removed in the normal state of the subdivision is left without being removed. The signal thus produced is divided into eight to obtain a new VC-3 clock that accommodates pointer fluctuation, and is provided to the elastic buffer 105 to raise the VC-3 signal.

As described above, the conventional smoothing PLL is composed of an analog PLL, which makes the H / W structure complicated and difficult to implement as a digital ASIC. However, the analog PLL portion is changed to a digital circuit using a smoothing shaking sequence. There is an advantage to simplify the circuit and ASIC.

Claims (1)

In the VC-3 signal extraction circuit of the SDH AU-3 having an elastic buffer 105, an overhead clock pulse canceller 101, and a bit leaking interval calculator 102, the 1-bit leaking interval calculator 102 The large section is determined by the request signal of the requester 103 of the 1-bit leaching requester 103 and the STM-1 clock by the output of the small bit, and the small section within the large section is determined at the time of the change of the rising or falling. And a signal for adding or removing a pulse to the clock synthesizer 104 to generate a smoothing clock according to the STM-1 clock, and to provide it to the elastic buffer 105 to the smoothing leaching sequence generator 201. And a 1-bit leaching sequence circuit of a management unit (AU-3) signal of a synchronous digital hierarchy (SDH).