KR960001272B1 - Enhanced bus interface parity checking circuit - Google Patents

Abstract

The circuit consists of a system bus which is connected with an upper module, an upper module whose interface is performed as field programmable gate array program and a program enable device which tests parity according to the receiving and the transmitting of data and address and is composed of an input and output unit which selects the input and the output of the data and the address between the system bus and the upper module, a data transmitting and receiving unit which outputs a value needed to transmit and to receive the data and the address in the input and output unit, and a parity testing unit which tests the parity bit of data transmitted from the data transmitting and receiving unit and to the upper module.

Description

Extended Bus Interface Parity Check Circuit

1 is a block diagram of the extended bus interface and parity check circuit of the present invention.

2 is a detailed block diagram of the data transceiver of FIG.

3 is a detailed configuration diagram of the parity check unit of FIG. 1.

* Explanation of symbols for main parts of the drawings

10: system bus 20: programmable device

21, 24: input / output unit 22: data transmission and reception unit

23: parity check unit 21A, 21B, 24A, 24B: input and output pad

22A, 22C: Logic Operators 22B, 22D: Flip-Flops

The present invention relates to a bus interface parity check circuit that involves transmission and reception of data or addresses. In particular, the parity check for data transmission and reception is programmed and integrated into a single chip, and the transmission / reception amount is expanded according to the improvement of the programmable device. An extended bus interface parity check circuit is provided.

In general, in the case of medium and large computers with a bus structure, the backplane board is used as the system bus, and the main processing unit, the main memory unit, the I / O processing unit, and the system control are used. A module (System Control Module) is used to exchange data with each other. Each of these units (hereinafter referred to as an upper module) includes an interface for transmitting and receiving to and from the system bus, and conventionally, when transmitting or receiving data or an address, it is mainly referred to as transistor-transistor logic (TTL). Several levels of chips were used together, and the parity check was also implemented using several chips at the transistor-transistor logic (TTL) level.

For example, a total of 32 transistor-transistor logic (TTL) s are used to transmit and receive 64-bit data from a central processing unit (CPU) board of a Tycom main computer.

Therefore, such a conventional technology has a problem in that the configuration of the circuit is complicated and the design area is large, and as a result of driving a plurality of chips, defects of each chip and noise or distortion from the signal transmission length appear.

In view of the above-described conventional problems, the present invention is capable of transmitting and receiving data of 64 bits or more using a single chip programmed in the interface unit of the upper module, and simultaneously configuring parity checks to the upper module. When designing, it reduces the design area and improves the stability of the system.

That is, the extended bus interface that implements the interface part of the upper module in the medium and large computer system having the bus structure as a programmable logic device having a high speed and a large capacity, and adds a data transmission and reception and a parity check part to the programmable logic device. To provide a parity check circuit.

When described in detail with reference to the drawings as follows.

As shown in FIG. 1, the extended interface parity check circuit of the present invention implements the upper interface unit 30 output interface unit connected to the system bus 10 as the programmable device 20, and the programmable device 20. Is configured to implement transmission and reception of data and addresses and parity checks thereof.

The programmable device 20 includes an input / output unit 21 and 24 installed in the input / output unit of the upper module 30 to select input / output of data and addresses between the system bus 10 and the upper module 30; A data transmission / reception unit 22 for outputting a value required by combining each input variable for transmitting and receiving data and addresses between the input / output units 21 and 24; And a parity check unit 23 for checking parity bits of data transmitted and received by the data transmission / reception unit 22.

As shown in FIG. 2, the data transmitting / receiving unit 22 includes logic operators 22A and 22C for combining and outputting five input variables (control signals and input / output data); And the flip-flops 22B and 22D for outputting data and addresses by synchronizing the outputs of the logic operators 22A and 22C with the clock signal CLK.

FIG. 3 is an example of the parity checker 23 of the present invention. Fifth to eighth logical units (A3, C3, A4, and C4) of which the fourth logical unit A1, C1, A2, and C2 and at least one input of the next higher three inputs are gated and output in a positive state, respectively; 9th through 12th logical products A5, C5, A6, and C6 each of which the at least one input of the top 3 inputs is positively gated and output, and each of the four logical products A1, C1, A2, C2 Each output (a, b, c, d) (h, i, j, k) (o, p, q, r) of (A3, C3, A4, C4) (A5, C5, A6, C6) At least one input using first to third NOR logic units A7, C7 and A8 and the outputs l, m and m that sequentially receive the input and provide the outputs (l, m, n). The first to fourth quadratic logical products A9, C9, A10, and C10 output and ended in this positive state, and The fifth to eighth quadratic logical spheres A11, C11, A12, and C12 outputted by inputting (1, m, n) at least one input to the negative state and outputting the first to fourth 2 First and second NOR logic units A13, which output the Z by outputting the outputs A, B, C, and D of the difference logical products A9, C9, A10, and C10, and the fifth to eighth. A second secondary logic logic unit C13 for outputting Z ′ by outputting the outputs A ′, B ′, C ′, D ′ of the secondary logic units A11, C11, A12, and C12, and Each of the outputs Z and Z 'of the first and second secondary logic units A13 and C13 transmits the control signal CONT1 and the respective T flip-flops B1, D1, B2 and D2 to the upper module 30. Logic operators (A14, C14, A15, C15) and T flip-flops (B1, D1) and (B2) configured to receive feedback signals from And an output unit 24 for providing each output (a) (b) of D2 to odd-level and even parity signals to the upper module 30.

In the drawing, (C), (D), and control signal CONT2 are shown in preparation for parity check implementation of data provided from the upper module 30 to the system bus 10.

Programmable device 20 according to the present invention performs an interface and parity check using a Programmable Gate Array (PGA) package, such a programmable device includes a Xilinx (XILINX) higher-order FPGA, the present invention Based on the design structure of the Xilinx FPGAs, the applicant has implemented a bus interface parity check circuit.

Referring to the operation and effects of the present invention configured as described above in detail.

First, when the data DATA 63 is received from the system bus 10 and the data 63 is inputted to the upper module 30, the input data data 63 receives the input / output pad 21A of the input / output unit 21. The data is transmitted to the inside of the transceiver 22.

At this time, when the input data (DATA 63) or address transfer, if the data (DATA 63) is connected to the B terminal of the logical operator 22A in the data transmission and reception unit 22 through the system bus 10, the logical operator In order to drive the output of the 22A, a control signal CNT1, which is output when the upper module 30 wants to receive data from the system bus 10, is output, and a flip connected to the A terminal of the logic operator 22A. This is the case when the output X of the output X of the flop 22B is low.

Here, since the initial state of the output X of the flip-flop 22B connected to the terminal A is low before the data DATA 63 is input from the system bus 10, the flip-flop 22B of the logic operator 2A is low. The signal entering) can be driven to "1".

On the other hand, when the signal entering the flip-flop 22B from the logic operator 22A enters the flip-flop 22B which is driven, the flip-flop 22B is synchronized with the clock CLK to set the output X to “1”. Drive X, the output X is transmitted to the upper module 30 through the input / output pad 24A of the input / output unit 24, and is fed back to the A terminal of the logic operator 22A and driven to “1”. It is.

Therefore, when the next clock CLK is input, the driving time of the output X of the flip-flop 22B is not driven since the drive is not driven by the signal “1” connected from the logic operator 22A to the flip-flop 22B. Is for one clock (CLK).

When the above-mentioned bar is represented by a formula, it is as following formula (formula 1).

X = D63 * CNT1 * ~ X * CNT2 * ~ d63. … … … … … … … … … … … … … … (Equation 1)

(* Is logic AND, ~ X is output (X) transmitted for one clock)

On the other hand, when receiving the data (data 63) from the upper module 30 and transmits the data (DATA 63) or address to the system bus 10, when the data (DATA 63) from the upper module 30 comes in, this input The data data 63 is transferred into the data transmission / reception unit 22 through the input / output pad 24A of the input / output unit 24.

At this time, if the input data (data 63) is connected to the E terminal of the logical operator 22A in the data transceiver 22, the output of the logical operator 22A connected to the flip-flop 22B is driven to a higher level. The control signal CNT2, which is sent out when the data is transmitted from the module 30 to the system bus 10, is driven, and the output X of the flip-flop 22B connected to the A terminal of the logic operator 22A is driven. If low.

Here, since the initial state of the output X of the flip-flop 22B connected to the terminal A is low before the data 63 is input from the upper module 30, the flip-flop 22B in the logic operator 22a is low. The signal entering) can be driven to "1".

On the other hand, when the signal entering the flip-flop 22B is driven from the logic operator 22A and enters the flip-flop 22B, the flip-flop 22B is synchronized with the clock CLK to set the output X to “1”. Drive X, the output X is transmitted to the system bus 10 through the input / output pad 21A of the input / output unit 21, and is fed back to the A terminal of the logic operator 22A and driven to “1”. do.

Therefore, the signal connected to the flip-flop 22B from the logic operator 22A when the next clock CLK comes in does not satisfy “data 1 * CNT2 * ˜X”, and thus the flip-flop at the next clock CLK. The output XC of 22B is not driven to "1".

That is, the time at which the output X of the flip-flop 22B is driven is for one clock CLK.

The bar described above is represented by the following formula (Formula 2).

X = d63 * CNT1 * ~ X * CNT1 * ~ D63... … … … … … … … … … … … … … … (Equation 2)

T-CNT2

When the data DTA 62 or the address is transmitted through the system bus 10 in the same manner, the output Y of the flip-flop 22D may be expressed as in Equation 3 below.

Y = D62 * CNT1 * ~ Y * CNT2 ~ d62... … … … … … … … … … … … … … … (Equation 3)

On the other hand, when the data (data 62) or the address is transmitted from the upper module 30, the output (Y) of the flip-flop (22D) can be expressed as shown in the following equation (Equation 4).

Y = d62 * CNT2 * ~ Y * CNT1 ~ D62... … … … … … … … … … … … … … … (Equation 4)

T = CNT2

The parity check according to the above operation will be described in detail with reference to FIG. 3 as follows.

First, each of the first through twelfth logical units A1, C1, A2, C2, A3, C3, A4, C4, A5, C5, A6, and C6 is made as follows.

a = D63 * ~ D62 * ~ D61

b = ~ D63 * D62 * ~ D61

c = ~ D63 * ~ D62 * D61

d = D63 * D62 * D61

h = D60 * ~ D59 * ~ D58

i = ~ D60 * D59 * ~ D58

j = ~ D60 * ~ D59 * D58

k = D60 * ~ D59 * D58

o = D57 * ~ D56 * ~ D55

p = ~ D57 * D56 * ~ D55

q = ~ D57 * ~ D56 * D55

r = D57 * D56 * D55

The respective input data [63]. 55] is the data or address coming from the system bus 10, and each of these bits is ANDed with several (3) data or address lines coming from the upper module.

The outputs (l, m, n) of the first to third NOR logic units A7, A8, C7, and C8 connected to the next stage are

l = ~ (a + b + c + d)

m = ~ (h + i + j + k)

n = ~ (o + p + q + r)

The output outputs the following values through the first to eighth secondary logic units A9, C9, A10, C10, A11, C11, A12, and C12.

A = l * ~ m * ~ n

B = ~ l * m * ~ n

C = ~ l * ~ m * n

D = l * m * n

A ′ = ~ l * ~ m * ~ n

B ′ = l * m * n

C ′ = l * ~ m * ~ n

D ′ = l * m * n

Meanwhile, the output values output the following values through the first and second secondary NOR logic units A13 and C13.

Z = ~ (A + B + C + D)

Z ′ = ~ (A ′ + B ′ + C ′ + D ′)

The above values are output through the logic operators A14, A15, C14 and C15 and the flip-flops B1, B2, D1 and D2 in conjunction with the control signal CONT1.

Ga = Z * CNT1 * ~ ga * ~ CNT2 * ~ Z ′

Me = Z′CNT1 * ~ me * ~ CNT2 * ~ Z

Here, outputs (a) and (b) indicate a case of transmission from the system bus 10 to the upper module 30, (a) indicates odd parity, and (b) even parity (EVEN Parity). ), The upper module 30 recognizes.

In the present invention, the parity check unit 23 indicates a case where the system bus 10 transmits the data to the upper module 30, and the parity check of data provided from the upper module 30 to the system bus 10 is performed by the system bus ( 10) and additionally implemented separately in the bus common system. Of course, in the present invention, the data parity check transmitted from the upper module 30 to the system bus 10 may be implemented with the principle and structure shown in FIG. 3 and such an implementation technique also belongs to the present invention.

Claims (2)

1. The upper module 30 interface unit connecting to the system bus 10 in a medium-to-large computer system having a bus structure is implemented by a programmable device 20 which is a Field Programmable Gate Array (FPGA), and the programmable device 20 is To implement parity check according to transmission and reception of data and addresses; The programmable device 20 includes input / output units 21 and 24 for selecting input and output of data and addresses between the system bus 10 and the upper module 30; A data transmission / reception unit 22 for outputting a value required by combining respective control variables inputted to transmit and receive data and addresses between the input / output units 21 and 24; And a parity checker (23) for checking parity bits of data transmitted from the data transceiver (22) to the upper module (30). The logic of claim 1, wherein the parity checker 23 performs first and fourth logics in which at least one of the upper three inputs is gated in a positive state through the input / output unit 21 on the system bus 10 and output. Fifth to eighth logical products (A3, C3, A4, and C4) of the multiplying unit (A1, C1, A2, C2) and at least one input of the next higher three inputs are output by being gated in a positive state. The ninth to twelfth logical products A5, C5, A6, and C6 outputted by an AND gated in a positive state, respectively, and each of the four logical products A1, C1, A2, and C2 (A3). Each output (a, b, c, d) (h, i, j, k) (o, p, q, r) from, C3, A4, C4) (A5, C5, A6, C6) is sequentially input The first to third NOR logic units A7, C7 and A8, which provide the output (l, m, n) by providing a gating, and the outputs (l, m, n) are input, and at least one input is in a positive state. First and fourth quadratic logical products A9, C9, A10, and C10 outputted by end-gating and outputting the outputs (l, m, n) The fifth to eighth quadratic logical units A11, C11, A12, and C12, and the first to fourth secondary logical units A9, C9, A first secondary NOR logic unit A13 for outputting Z by outputting the outputs A, B, C, and D of A10 and C10, and the fifth to eighth secondary logic units A11, C11, A second secondary logic logic unit C13 for outputting Z 'by outputting the outputs A', B ', C', and D 'of A12 and C12, and the first and second secondary logic units T-flips receiving the respective outputs Z and Z 'of the A13 and C13, the transmission control signal CONT1 to the upper module 30, and the feedback signals of the respective T flip-flops B1, D1, B2 and D2, respectively. Logic operators A14, C14, A15, C15 and the respective outputs of the T flip-flops B1, D1 and B2, D2, which are configured to provide sequential selection to the flops B1, D1, B2, D2, 2) an extended bus interface comprising an input / output unit 24 for providing the upper module 30 to recognize odd and even parity signals. Parity check circuit.