KR960001270B1 - Communication control circuit with redundancy - Google Patents

Abstract

a local memory; a common memory connected between a common address bus and a common data bus; a first buffer for connecting the common address to the local address bus; a second buffer for connecting the common data bus to the local data bus; a third buffer for connecting the common address bus to a VME address bus; a fourth buffer for connecting the common data bus to a VME data bus; a first central processing unit for accessing the local memory and the common memory through the first and second buffers; a second central processing unit for accessing the common memory through the third and fourth buffers and commonly sharing data with the first central processing unit; a bus error controller for generating an error signal until an upper data strobe signal is set; a data error transmission recognition generator for generating a bus error signal; a bus mediator for applying a data transmission recognition signal and the bus error signal to a master unit of the first and second central processing units; a bus controller for providing control signals to the VME bus; and a control signal generator for generating control signals and enabling the second buffer through the input signals.

Description

Communication control circuit with redundancy

1 is a redundant configuration diagram of a communication control circuit according to the present invention.

2 is an explanatory diagram of VME bus arbitration between redundant processors according to the present invention.

3 is a block diagram of a communication control circuit having redundancy according to the present invention.

4A and 4B are detailed circuit diagrams of one embodiment of FIG.

5A to 5D are operation timing diagrams of respective parts of FIGS. 4A and 4B.

6 is a memory map diagram of the present invention.

* Explanation of symbols for main parts of the drawings

10,12: 1st, 2nd CPU 14-20: 1st-4th buffer unit

22: bus arbitration unit 24: bus error control unit

26: bus control unit 28: data transmission signal generator

30: local memory 32: common memory

34: control signal generator

TECHNICAL FIELD The present invention relates to a communication control system, and more particularly to a circuit for controlling communication between redundant processors having redundancy.

In general, a communication system such as a remote comprehensive information system requires rapid processing of a large amount of data between a higher system and a lower system.

And by improving the reliability of data processing, master and slave are duplicated to send and receive information between processors, so that when the master controller malfunctions, the other slave controller can execute commands on its behalf. A circuit is needed.

Accordingly, an object of the present invention is to provide a communication control circuit having redundancy so that hardware can control communication between processors that are identical and functionally shared with each other.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a redundant configuration diagram of a communication control circuit according to the present invention. The present invention has a redundancy configuration as shown in FIG. 1 to increase the reliability of the controller. That is, the first and second controllers 2 and 6, which are dualized in an active / stand-by structure, are placed in a standby state and one is in a standby state, and the other is in a standby state. When an error occurs in the central processing unit (hereinafter referred to as “CPU”), the CPU, the processor of the waiting controller, performs the function. In this case, separate communication channels 103 and 104 are required between the two CPUs. In the present invention, communication between the two CPUs is enabled using the shared common memory 4 and 8, and the slave accesses the master in a configuration in which the master accesses the slaves. can do. In addition, since the processor, that is, CPU redundancy uses a separately configured Versa Module Euro (VME) bus memory, communication between each CPU of the first and second controllers 2 and 6 using the VME bus 101 using a common bus. Makes this possible. In addition, the VME bus 101 is composed of a data transfer bus (hereinafter referred to as "DTB"), a priority interrupt bus, a data arbitration bus, and a utility bus. The VME bus 101 includes a high speed asynchronous parallel data transfer bus.

FIG. 2 is an explanatory diagram of the arbitration of the VME bus between the redundant processors according to the present invention, which shows that the level # 3 ”of the bus arbitration levels defined in the VME bus is used. The first and second CPUs 10 and 12 of FIG. 2 are processors of the first and second controllers 2 and 4 of FIG. 1, respectively, and communicate with each other using the VME bus 101. At this time, since the bus arbitration level “3” is used, the bus request signal is BR3 *, the bus permission signals are BG3IN *, BG3OUT *, and BBSY * is the bus busy signal.

3 is a block diagram of a communication control circuit having redundancy according to the present invention, which includes a local memory 30 connected to a local address bus 201 and a local data bus 202, and a shared address. It is connected between the common memory 32 connected to the bus 203 and the shared data bus 204 and the shared address bus 203 and the local address bus 201 and is enabled by the control of the bus mediation section 22. (enable) is connected between the first buffer unit 14, which connects the shared address bus 203 and the local address bus 201, and the shared data bus 204 and the local data bus 202, and the control signal generator Enabled by the control of 34, between the second buffer unit 16, which connects the shared data bus 204 and the local data bus 202, between the VME address bus 205 and the shared address bus 203. Connected and enabled by the control of the bus arbitration unit 22, so that the shared address bus 204 and the VME address are The third buffer unit 18 which connects the bus 205 and the VME data bus 206 and the shared data bus 204 are connected to each other and are enabled by the control of the bus mediation unit 22 to enable the shared data bus ( 204 and the fourth buffer unit 20 for connecting the VME data bus 206 and the local memory 30 and the first and second buffer units 14 and 16 through the local buses 201 and 202, The common memory 32 is accessed through the first and second buffer units 14 and 16 when the local memory 30 is accessed and the bus request signal BG3IN * is input by making a bus request to the shared buses 203 and 204. The first CPU 10, which is a processor that accesses the CPU, and the first CPU 10 are dualized with each other in an active / standby state to operate as a master and a slave, and are operated through the VME buses 205 and 206. 3, the fourth buffer unit (18, 20) is connected, the bus request for the shared bus (203, 204) to the bus use permission signal BG3IN * input when the third, fourth buffer unit (18, 20) The second CPU 12, which is a processor that accesses the common memory 32 and shares data with the first CPU 10, and the first and second CPUs 10 and 12 are the common memory 32 and the local memory 30. If the upper data strobe signals LLUDS * and SLUDS * generated by the corresponding CPU do not terminate until the set time elapses, the bus error controller 24 generates an error signal. Whether data transfer is indicative of the termination of bus occupancy for the corresponding bus between shared bus (203, 204) and local bus (201, 202) after a certain time delay from the time when strobe signals LLUDS * and SLUDS * are generated. When the signal DTACK * is generated, when the error signal is generated from the bus error controller 24 before the DTA CD signal DTACK * is generated, the DTACK signal that generates the bus error signal BERR * indicating the error of the corresponding bus. Occur (28) and control signals on the VME buses 205 and 206 to monitor the bus signals of the first and second CPUs 10 and 12 to the shared buses 203 and 204 when the VME buses 205 and 206 are in an idle state. In response, the bus enable permission signal BG3IN * is applied to the corresponding CPU to permit bus use, and a master enable signal for selectively specifying access of the first and second CPUs 10 and 12 to the common memory 32. MASTENN * is generated and correspondingly enable the first, third, and fourth buffer units 14, 18, and 20, and the DTACK signal DTACK * and the bus error signal BERR * are inputted to generate the first and second CPUs. 10 and 12, the bus arbitration unit 22 which is applied to the CPU which is the master, and the bus control unit 26 which connects the control signals of the local buses 201 and 202 to the VME buses 205 and 206 according to the master enable signal MASTENN *. Control for controlling read / write of the local memory 30 and the common memory 32 under the control of the first and second CPUs 10 and 12 and the bus intermediate unit 22. The control signal generator 34 generates the calls and applies them to the local memory 30 and the common memory 32 and enables the second buffer unit 16.

4A and 4B show detailed circuit diagrams of one embodiment of the remaining portions except for the first and second CPUs 10 and 12 in FIG.

4A shows details of the third and fourth buffer units 18 and 20, the bus arbitration unit 22, the bus error control unit 24, the bus control unit 26, and the DTACK signal generation unit 28 in FIG. A schematic is shown. The third buffer unit 18 is connected between SA1-SA23 corresponding to the shared address bus 203 of FIG. 3 and XA1-XA23 corresponding to the VME address bus 205. The fourth buffer unit 20 is connected to the SD0-SD15 corresponding to the shared data bus 204 of FIG. 3 and the XD0-XD5 corresponding to the VME data bus 206. The bus arbitration unit 22 is composed of first and second bus arbitration modules 46 and 48 using a gate array logic (GAL), and the bus error control unit 24 includes four counters 50-56. The bus control unit 26 includes a bus control module 58 and a buffer 60 using the GAL, and the DTACK signal generator 28 uses the GAL.

4B shows a detailed circuit diagram of the first and second buffer units 14 and 16, the local memory 30, the common memory 32, and the control signal generator 34 of FIG. 3. The first buffer unit 14 includes three buffers 36-40 connected between SA1-SA23 corresponding to the shared address bus 203 of FIG. 3 and LA1-LA23 corresponding to the local address bus 201. Configure. The second buffer unit 16 includes two buffers 42 and 44 connected between the SD0-SD15 corresponding to the shared data bus 204 of FIG. 3 and the LD0-LD15 corresponding to the local data bus 202. Configure.

The local memory 30 is composed of RAM 62 and ROMH ROM 64 connected to LA1-LA23 corresponding to the local address bus 201 of FIG. 3 and LD0-LD15 corresponding to the local data bus 202. . The common memory 32 includes two RAMs 66 and 68 connected to SA1-SA23 corresponding to the shared address bus 203 of FIG. 3 and SD0-SD15 corresponding to the shared data bus 204. The control signal generator 34 uses GAL.

The logic of the first and second bus arbitration modules 46 and 48, the DTACK signal generator 28, the bus control module 58 and the control signal generator 34 using the GAL in FIGS. 4A and 4B. The logic equation is as described later.

5A to 5D are operation timing diagrams of the respective parts of FIGS. 4A and 4B, and FIG. 5A is an operation timing diagram of the bus arbitrator 22, and FIG. 5B is an operation of the DTACK signal generator 28. FIG. 5c is an operation timing diagram in which the bus error signal BERR * is generated by the DTACK signal generator 28 in response to the occurrence of an error signal in the bus error controller 24, and FIG. 5d is a timing diagram of the bus error controller 24. Counting motion timing.

6 illustrates a memory map according to the first and second CPUs 10 and 12.

Hereinafter, an operation of an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

First, the first and second CPUs 10 and 12 of FIG. 3, which communicate with each other as shown in FIG. 2, use a DTB through a master to exchange information by selecting a slave memory and an I / O device. At this time, data transmission is performed by an asynchronous interlock method. The data transfer between the master side and the slave side is not performed by the system clock but by the DTACK signal DTACK * of the terminal LDTACKN of the first bus arbitration module 46 as shown in FIG. 4A on the slave side. In other words, unless the slave returns the DTACK signal DTACK *, the master does not end the data transfer cycle. In the present invention, only D00-D15 (16 bits) is used in the data line, and in the write cycle, the DTACK signal DTACK * is driven to a "low" state to indicate that the slave has successfully received data, and in the read cycle, the data bus Drive to "low" state to indicate that data has been loaded on the phase.

The bus error signal SBERR * of the terminal 02 of the DTACK signal generator 28 is driven low by the bus error controller 24, which is a slave or a bus timer, to inform the master of the failure of data transmission.

The second bus arbitration module 48 of the bus arbitration unit 22 is a module that requests a bus to access the bus from each CPU of the VME bus system, and uses the release when Done (RWD) method as a bus request method. do. The RWD method is a method in which a bus is released after the CPU accesses the bus after the required time has passed.The master requests a bus for the VME bus and when the access is granted, the master accesses the slave by connecting the CPU internal bus and the DTB of the VME. Do it.

At this time, the bus control module 58 of the bus control unit 26 functions to drive signal lines such as address bus, AM code, AS *, DS1 *, DS0 *, WR *, and the like, which initiate a data transfer cycle on the data bus. Branch is a module. The signal XWR * of the terminal B1 of the buffer 60 of the bus control unit 26 is also used by the master to indicate the direction of the data transfer operation. When the signal XWR * is driven low, the data transfer direction is from master to slave, and when it is high, from slave to master.

In the minimum configuration of the VME bus system, there is only one DTB master in the system on the bus, but the bus usage of each master capable of two controllers 2 and 6 as shown in FIG. 1 is coordinated by the first bus arbitration module 46. The communication between the first and second CPUs 10 and 12 uses the common memory 32 to exchange information by viewing each CPU's desired information and causing a bus interrupt to read this information from another CPU.

The second bus arbitration module 48 of the master and slave adopts a method of occupying the bus each time the bus is requested, thereby giving equal priority to each bus request signal. The signal allocation according to the bus request for each CPU is shown in FIG. Among the signals of FIG. 2, the bus request signal BR3 * is commonly used by the first and second CPUs 10 and 12, and the bus arbitration is performed by the daisy chain method using the bus permission signals BGOIN * and BGOOUT *. Do

The CPU of the master among the first and second CPUs 10 and 12 exchanges data with the slave CPUs through the VME buses 205 and 206 using the first through fourth buffer units 14-20 and the buffer 60. In order to receive the license of the VME bus from the first bus arbitration module 46, that is, the "low" state of the master enable signal MASTENN *. The master must use this signal to control the DTB control signal to meet the requirements of the VME bus.

In addition, the present invention employs a single level arbiter (SGL) method. The logic function equations of the DTACK signal generator 24, the second bus arbitration module 48 and the bus control module 58 will be described next. The circuits operate in conjunction with the first bus arbitration module 46 to request bus VME buses 205 and 206 and to provide bus arbitration between boards using the same bus request signal BR3 * by means of a daisy chain of bus permission signal BR3IN *. To perform. In the case of using the VME buses 205 and 206 in the first and second CPUs 10 and 12, the IACKVME is generated when the VMENN * signal is generated and the interrupt ACK signal is generated when the data is written to the common memory 32. It is time to generate a signal. In both cases, the second bus arbitration module 48 generates the bus request signal BR3 * (XBR3 * in FIG. 4A) and activates the bus busy signal BBSY * as a bus usage indication when the bus occupancy signal BG3IN * is received. Drive to the bus and access the bus. When bus request signal BR3 * is not activated and bus permission signal BG3IN * is received (“low” state), it is transferred to the next board to enable the VME bus (205, 206) on the next board. The timing at this time is the same as that of FIGS. 5A and 5B.

In the bus error controller 24, the upper data strobe signal generated from the CPU as the first CPU 10 accesses the local memory 30 or the first and second CPUs 10 and 12 access the common memory 32. If LLUDS * is not terminated until the set time has elapsed, an error signal is generated and applied to the DTACK signal generator 28. At this time, when the error signal is generated by the bus error control unit 24 before the DTACK signal DTACK * is generated, the DTACK signal generator 28 generates bus error signals BERR * and SBERR * indicating errors of the corresponding bus. This bus error signal SBERR * is applied to the CPU via the first bus arbitration module 46. That is, as shown in FIG. 5C, when the specific address starts to be accessed and waits for the DTACK signal DTACK * for up to 160 μs, and there is no DTACK * signal DTACK *, the bus error signal BERR * is set to “low” and the first and second CPUs 10, Inform 12 that a bus error has occurred.

In order for the first and second CPUs 10 and 12 to use the common memory 32 through the VME buses 205 and 206, the first and second CPUs 10 and 12 monitor the control signals on the VME buses 205 and 206. . Otherwise, data conflicts occur because other subunits use the common memory 32 simultaneously. To avoid this phenomenon, the second bus arbitration module 48 notifies the idle state on the VME buses 205 and 206.

Next, the control of the VME data bus 206 shows that the fourth buffer unit 20 is controlled by the terminals DDIR and DSEN of the first bus arbitration module 46. If the DDIR signal is "high", the board controls the VME bus. The VMENN * signal is used as an enable signal for the fourth buffer unit 20 for the data of the VME data bus 206. The control of the fourth buffer unit 20 is controlled by the VMEENN * signal and the MASTENN * signal. These signals determine the enable of the third buffer unit 18 with respect to the address of the VME address bus 205 and are also responsible for the control of the common memory 32.

The control signal generator 34 generates various memory control signals. The CPU has three access spaces: local memory, 10, internal common memory, and VME memory. The internal common memory operates in dual port mode, accessible by the local CPU and by another VMEmaster. Therefore, control signals are also divided into local memory 30 and common memory 32. In FIG. 4B, signals are divided into "L" for local memory 30 and "S" for common memory 32. .

First of all, the LOE * (Local Output Enable) signal among the control signals for the local memory 30 is a read strobe signal of memory and I / O. When the WR * signal of the CPU is “high” and the LDS * signal or the UDS * signal is set, Is generated. However, during the interception response cycle, the LOE * signal is delayed by a separate signal called Local Write Enable (LWEN) to allow sufficient time for the device requesting the interception to receive the interception acknowledgment signal and generate a vector. I'm making it. The LEEL * (Local Write Enable Low) signal and the LWEH * (Local Write Enable High) signal are write strobe signals used as control signals for the low byte (base address) and high byte (excellent address), respectively. In the CPU, data is outputted even when writing by byte. Therefore, it is necessary to give a write signal to the memory or I / O by dividing the high and low bytes. In addition, certain I / Os require a sufficient data hold time to write, so use a write enable signal called the LWEN signal to terminate the write strobe pulse for the memory in the presence of data on the data bus before chip selection is terminated. Doing.

Next, the SOE * (Shared Output Enable) signal SWEL * (Shared Write Enable Low) signal and SWEH * (Shared Write Enable High) signal, which are control signals for the common memory 32, are LOE * signal, LWEL * signal, and LWEH * signal. Same use as, and made in a similar way. However, the SWR * signal, the SUDS * signal, and the SLDS * signal are used together as the control signal input, which is a bus control module that controls the access direction of the common memory 32 to the LWR * signal, the LUDS * signal, and the LLDS * signal. The master enable signal MASTENN * signal of the terminal 13 of 58 is masked. At this time, if the master enable signal MASTENN * is "low", the local CPU accesses the RAMs 66 and 68 of the common memory 32. If the master enable signal MASTENN * is "low", the external VME master accesses the RAMs of the common memory 32. To access it. The SWR * signal, SLDS * signal, and SLUDS * signal are made from the WR * signal, LDS * signal, and UDS * signal output from the local CPU when the master enable signal MASTENN * is "low", and the VME when "high". It is a bidirectional signal made from the XWR signal, the XDSO * signal, and the XDS1 * signal entering the buses 205 and 206. The SLUDS * signal is a logical sum signal of the SLDS * signal and the SUDS * signal. The SDEN * (Shared Data Enable) signal is used to enable the shared bus side data buffer when accessing the internal and external common memory.

Looking at the generation of the local DTACK signal and the bus error signal in the DTACK signal generator 28, since the CPU adopts the asynchronous data transmission method, the access cycle ends when the DTACK signal is received from the slave to the master. Since the memory or I / O can be classified into various types according to the access speed, the delay width of the DTACK signal should be changed accordingly. The differentialization of the DTACK signal to the local memory 30 is achieved by delaying the 8 MHz CPU clock CPU CLK by the shift register inside the DTACK signal generator 28, which is a LLUDS * signal that is a local upper data strobe signal. It is activated by a signal and delayed by one clock (125 µ) for each step. The DTACK for RAM is delayed by up to 125μs after applying the LLUDE * signal, the ROM is delayed by 250μs, the I / O by 375μ, and the delay in response is 500μs. In any case, if the DTACK signal is not applied within 125ms, the counters 50-56, which are timers for applying the signal from the bus to the CPU, are considered bus timeout. The counter 50-56 is a dual 4-bit counter that is clocked when the E clock ECLK of a CPU having a frequency of 800 KHZ is cleared and is cleared when the LLUDS * signal is "high". The second counters 52 and 56 are received from the output terminals QD1 of the first counters 50 and 54, as shown in FIG. 5D, and the output terminals WD2 of the second counters 52 and 56 become “high”. Since the BERR * signal is applied to the CPU at the moment, the time until the LLUDS * signal is applied and the BERR * signal is generated is as follows.

[Equation 1]

Tberr = 1.25 ms x 16 (4 bits) x 8 (3 bits) = 160 ms. … … … … … … … … (One)

The LWEN * (Local Write Enavle) signal is used to invert the DTACK signal to ensure data hold time when writing to I / O or RAM.

The shared DTACK signal and the bus error signal, the SDTCK * signal and the SBERR * signal, are generated in the same way as the LDTCK * signal and the LBERR * signal. However, the input is a SLUDS * signal, not a LLUDS * signal. The SLUDS * signal, like the SUDS * signal and the SLDS * signal, is provided by the local CPU when the local CPU accesses the internal common memory 32, and accessed by other VME masters. Provided by the VME master. However, since the common memory 32 is only the RAM 66 and 68, it is not necessary to allocate various delay times as in the local memory case. Like the LWEN * signal, the SWEN * signal is used to terminate the write strobe signal first before the data transfer ends.

The MASINV signal of the terminal 01 of the bus control module 58 of the bus control unit 26 is an inverted MASTEN * signal and is used as an enable signal of the buffer 60 for the VME address. The SAM0-SAM2 signal is an address correction signal that is input to AM0-AM2 and output to XAM0-XAM2. The SLDS * signal and the SUDS * signal are bidirectional signals. When output to the VME side, the BLDS * signal and the BUDS * signal, which are signals masked by the DSEN * signal of the terminal DSENN of the first bus arbitration module 46, are outputted. When input from the bus, the XDSO * and XDS1 * signals are input to BLDS * and BUDS * and output as SLDS * and SUDS * signals. The DS1 signal is an active "high" signal in which the SLDS * signal and the SLDS * signal are ORed together, and are input to the first bus arbitration module 46.

Among the control signals for the internal common memory 32, the SOE * (Shared Output Enable) signal, SWEL * (Shared Write Enable Low) signal, and SWEH * (Shared Write Enable High) signal are supplied to LOE *, LUDS *, and LLDS. The MASTEN * signal that controls the access direction of the memory 32 is masked. If the MASTEN * signal is "low", the local CPU accesses the internal common memory 32, and if it is "high", the external VME master accesses the internal shared memory. The SWR * signal, SLDS * signal, and SLUDS * signal are generated from the WR * signal, LDS * signal, and UDS * signal output from the local CPU when the MASTEN * signal is "low", and enters the VME bus when "high". Is a bidirectional signal generated from the XWR * signal, the XDSO * signal, and the XDS1 * signal. The DSEN * (Shared Data Enable) signal is used to enable the shared bus side data buffer when accessing the internal and external common memory.

As described above, the present invention can control a communication between duplicated processors using a common memory to process a large amount of data quickly, and improve reliability by having redundancy by sharing data between two processors.

Claims (1)

A communication control system, comprising: a local memory connected to a local address bus and a local data bus, a common memory connected to a shared address bus and a shared data bus, and connected between the shared address bus and the local address bus, and to a predetermined control. A first buffer means connected to the shared address bus and the local address bus, and connected between the shared data bus and the local data bus and enabled by a predetermined control to enable the shared data bus and the local data bus. A first buffer means for connecting a second buffer means connected between the shared address bus and the local data bus and enabled by a predetermined control to connect the shared data bus and the local data bus, and a VME address bus; Connected between the shared address buses and enabled by predetermined control A third buffer means for connecting the shared address bus and the VME address bus, and a fourth buffer connected between the VME data bus and the shared data bus and enabled by predetermined control to connect the shared data bus and the VME data bus. Means, connected to the local memory and the first and second buffer means via the local bus, accessing the local memory, and making a bus request for the shared bus to input the bus permission signal. A first central processing unit that is a processor accessing the common memory through a second buffer means, and the first central processing unit and the first central processing unit are duplexed into one state different from each other in active / standby mode and relatively operate as a master and a slave; Is connected to the third and fourth buffer means through the VME bus, and requests a bus for the shared bus to input the bus permission signal. A second central processing apparatus which is a processor for accessing the common memory through the third and fourth buffer means and sharing data with the first central processing apparatus; and the first and second central processing apparatuses being connected to the common memory. Bus error control means for generating an error signal when the upper data strobe signal generated from the central processing unit does not terminate until the set time has elapsed as the local memory starts to access the corresponding memory, and the upper data strobe signal. Generates a data transmission signal indicating the end of the bus occupancy for the corresponding bus among the shared bus and the local bus after a predetermined time delay from the time point at which the signal is generated, and from the bus error control means before generating the data transmission signal. When the error signal is generated, a bus error signal indicating an error of a corresponding bus is generated. Monitoring the control signals on the VME bus and permitting the bus to be used in response to a bus request of the first and second central processing apparatuses for the shared bus when the VME bus is idle. A signal is applied to the central processing unit to permit the use of a bus, and generates a master enable signal for selectively specifying access of the first and second central processing units to the common memory; Bus mediation means for correspondingly enabling the third and fourth buffer means and inputting the data transmission acknowledgment signal and the bus error signal to a central processing unit which is a master among the first and second central processing units; Bus control means for connecting control signals of the local bus to the VME bus according to an enable signal, and for control of the first and second central processing apparatuses and the bus mediation means. And generating control signals for controlling read / write of the local memory and the common memory, applying the control signals to the local memory and the common memory, and enabling the second buffer means. Communication control circuit with redundancy.