KR960000369B1 - Fine contact hole forming method of semiconductor device - Google Patents

Fine contact hole forming method of semiconductor device Download PDF

Info

Publication number
KR960000369B1
KR960000369B1 KR1019920014860A KR920014860A KR960000369B1 KR 960000369 B1 KR960000369 B1 KR 960000369B1 KR 1019920014860 A KR1019920014860 A KR 1019920014860A KR 920014860 A KR920014860 A KR 920014860A KR 960000369 B1 KR960000369 B1 KR 960000369B1
Authority
KR
South Korea
Prior art keywords
photoresist
size
pattern
molecular weight
silane compound
Prior art date
Application number
KR1019920014860A
Other languages
Korean (ko)
Other versions
KR940004835A (en
Inventor
강호영
Original Assignee
삼성전자 주식회사
김광호
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자 주식회사, 김광호 filed Critical 삼성전자 주식회사
Priority to KR1019920014860A priority Critical patent/KR960000369B1/en
Publication of KR940004835A publication Critical patent/KR940004835A/en
Application granted granted Critical
Publication of KR960000369B1 publication Critical patent/KR960000369B1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

forming a photo-register pattern on a semiconductor substrate according to a general etching process; and reducing the size of a display window formed between the photo-register by means of a compound to increase the bulk of the photo-register by increasing the molecular weight of the photo-register

Description

미세 접촉창 형성방법How to form a fine contact window

제1도는 통상의 사진 식각 방법 및 본 발명의 의하여 형성된 포토레지스트 패턴과 패턴사이에 형성된 표시창을 나타낸 단면도.1 is a cross-sectional view showing a conventional photolithography method and a display window formed between a pattern and a photoresist pattern formed by the present invention.

제2도는 마스크의 크기와 패턴사이의 상관 관계를 나타낸 그래프도.2 is a graph showing the correlation between the size of the mask and the pattern.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 부피가 증가된 포토레지스트1: photoresist with increased volume

2 : 통상적인 사진식각에 의하여 형성된 포토레지스트2: photoresist formed by conventional photolithography

3 : 기판 5 : 2에 의하여 형성된 표시창의 크기3: size of display window formed by substrate 5: 2

5′: 1에 의하여 형성된 표시창의 크기5 ′: size of 1 shaped display window

이 발명은 반도체 제조시의 사진식각 공정에서 미세 접촉창을 형성하는 방법에 관한 것으로, 더욱 상세하게는 고집적화용 반도체 기억소자의 제조에 유용한 미세 접촉창 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a micro contact window in a photolithography process during semiconductor manufacturing, and more particularly, to a method for forming a micro contact window useful for manufacturing a highly integrated semiconductor memory device.

최근 반도체 기억 소자의 고집적화 추세에 따라 고집적화용 반도체 기억소자를 제조하는 방법에 관하여 다양한 연구들이 행해지고 있으며, 예를 들면 대한민국 특허공고 제90-8649호에는 축적 전극들간의 펀치드루(punch-through) 현상을 제거하여 트랜치 커패시터들을 근접시킬수 있는 소형화 반도체 메모리장치가, 대한민국 특허공고제91-246호에는 소자들을 반도체 기판상에 고밀도로 집적하기 위한 디램 셀 어레이가 개시되어 있다.Recently, according to the trend of high integration of semiconductor memory devices, various studies have been conducted on the method of manufacturing highly integrated semiconductor memory devices. For example, Korean Patent Publication No. 90-8649 discloses a punch-through phenomenon between storage electrodes. A miniaturized semiconductor memory device capable of removing trenches by proximity to trench capacitors is disclosed. Korean Patent Publication No. 91-246 discloses a DRAM cell array for densely integrating devices onto a semiconductor substrate.

종래의 반도체 제조방법에서는 사진식각 공정 동안에 포토마스크의 크기를 변화시킴으로써 접촉창의 크기를 조절하였으나, 이 경우에는 빛의 회절현상에 의하여 형성할 수 있는 크기에 한계가 있고 마스크 크기를 변화시키면 일반적으로 접촉창의 크기가 큰 경우에는 마스크 크기에 비례하여 변하지만 최소 크기 이하에서는 더 커지는 문제가 있다.In the conventional semiconductor manufacturing method, the size of the contact window is controlled by changing the size of the photomask during the photolithography process, but in this case, there is a limit to the size that can be formed by the diffraction of light. If the window size is large, it changes in proportion to the mask size, but there is a problem that the window size is larger than the minimum size.

즉, 종래의 방법에 의하면 기판에 투영되어 형성된 패턴의 크기는 마스크의 패턴 크기와 투영에 사용한 광의 파장 투영 렌즈에 의해 결정이 된다.That is, according to the conventional method, the size of the pattern projected onto the substrate is determined by the pattern size of the mask and the wavelength projection lens of the light used for the projection.

일반적으로 패턴이 클 경우에는 마스크 패턴의 크기를 따르나 마스크 패턴 크기가 작아질 경우에 최소 패턴의 크기는 하기 식에 따라서 파장과 렌즈의 구경비에 의해 결정이 된다. 따라서 최소 크기 이하에서는 마스크의 크기가 작아질수록 패턴이 커지게 된다(제2도참조).In general, when the pattern is large, the size of the mask pattern depends on the size of the mask pattern. However, when the size of the mask pattern is small, the size of the minimum pattern is determined by the wavelength and the aperture ratio of the lens according to the following equation. Therefore, below the minimum size, the smaller the size of the mask, the larger the pattern (see FIG. 2).

[수학식 1][Equation 1]

(상기 식에서 K는 공정 매개 변수로서 0.6~1.0이며,λ는 투영에 사용한 광의 파장이며, NA는 렌즈의 구 경비이다.) 마스크 크기와 패턴 크기의 상관 관계를 제2도에 그래프로써 나타내었다.(K is 0.6 to 1.0 as the process parameter, λ is the wavelength of light used for the projection, and NA is the sphere diameter of the lens.) The correlation between mask size and pattern size is shown graphically in FIG.

이상과 같은 원리에 의해 형성하고자 하는 패턴의 크기를 파장과 렌즈에 의해 변화시켰으나 아주 작은 패턴의 형성에는 어려움이 있었고, 더구나 접촉창의 크기는 일반 패턴의 크기에 비해 훨씬 큰 것만을 형성할 수 있었다.According to the principle described above, the size of the pattern to be formed was changed by the wavelength and the lens, but it was difficult to form a very small pattern. Moreover, the size of the contact window was much larger than that of the general pattern.

그러나 집적도가 높아지면서 기타 패턴의 크기보다 접촉창의 크기를 감소시키는 것이 보다 중요하게 되었다.However, as the density increases, it is more important to reduce the size of the contact window than the size of other patterns.

이 발명은 상기한 바와 같은 점을 고려하여 안출된 것으로서, 사진 식각 공정을 사용하여 형성 할 수 있는 접촉창의 크기를 접촉창 형성후에 감소시키므로써 반도체 기억소자의 고집적화를 이루는 것을 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made in view of the above point, and aims to achieve high integration of semiconductor memory devices by reducing the size of a contact window that can be formed using a photolithography process after formation of the contact window.

이와 같은 목적을 달성하기 위하여, 이 발명은 일반적인 사진식각 공정을 사용하여 반도체 기판상에 감광액 패턴을 형성한 뒤, 여기에 감광액의 부피를 증가시킬수 있는 물질로서 실란화합물을 고온 분무에 의해 첨가하여 접촉창의 면적을 감소시키는 것을 특징으로하는 미세 접촉창 형성 방법이 제공 된다.In order to achieve the above object, the present invention forms a photoresist pattern on a semiconductor substrate using a general photolithography process, and then adds a silane compound as a substance capable of increasing the volume of the photoresist by hot spraying. There is provided a method for forming a fine contact window, characterized in that to reduce the area of the window.

상기 실란화합물의 예로는 헥사메틸디실라제인(HMDS), 테트라메틸디실라제 (TMDS), 트리메틸실릴디에틸아민(TMSDEA), 디메틸실릴디에틸아민(DMSDEA), 헥사메틸사이클로트리실라제인(HMCTS)등을 들 수 있다.Examples of the silane compound include hexamethyldisilazane (HMDS), tetramethyldisilase (TMDS), trimethylsilyldiethylamine (TMSDEA), dimethylsilyldiethylamine (DMSDEA), hexamethylcyclotrisilasein (HMCTS ), And the like.

실란화합물이 감광액의 부피를 증가시키는 원리는 예를 들어 하기 식으로 나타내어질 수 있다.The principle by which the silane compound increases the volume of the photosensitive liquid may be represented, for example, by the following formula.

[반응식 1]Scheme 1

대부분의 감광액은 상기 식과 같이 페놀 구조를 가지고 있으므로 예컨대 160~180℃의 고온에서 예컨대 헥사메틸디실리제인을 첨가하면 OH기가 치환되어 Si(CH3)3를 가지게 된다. OH기에 비하여 O-Si(CH3)3기의 부피가 훨씬 크기 때문에 전체적으로 부피가 약 30~50% 정도 증가 한다. 이에 의하여, 통상적인 사진 식각의 방법에서 얻어지는 0.5㎛의 접촉창(5)의 크기가 0.1㎛이상 감소되어 0.35㎛ 크기(5′)까지 가능하게 된다.Since most photoresists have a phenol structure as described above, when hexamethyldisilisane is added, for example, at a high temperature of 160 to 180 ° C., an OH group is substituted to have Si (CH 3 ) 3 . As the volume of O-Si (CH 3 ) 3 groups is much larger than that of OH groups, the volume increases by about 30 to 50%. As a result, the size of the 0.5 μm contact window 5 obtained by the conventional method of photolithography is reduced by 0.1 μm or more, allowing up to 0.35 μm size (5 ′).

이하 도면을 참고로 하여 본 발명의 바람직한 실시 양태를 설명하기로 한다. 제1도는 통상의 사진식각 방법 및 본 발명의 방법에 의하여 형성된 포토레지스트 패턴과 패턴사이에 형성된 표시창을 나타낸 도면이며, 제2도는 마스크의 크기와 패턴사이의 상관 관계를 나타낸 그래프도이다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. 1 is a view showing a conventional photolithography method and a display window formed between a photoresist pattern and a pattern formed by the method of the present invention, and FIG. 2 is a graph showing a correlation between a size and a pattern of a mask.

통상의 사진식각의 방법에 의하여 실리콘 웨이퍼 기판상(3)에 포토레지스트패턴(2)를 형성하였다. 이에 의하여 형성된 포토레지스트패턴(2)은 포토레지스트 사이의 표시창이 0.5㎛의 크기(5′)를 갖었다. 형성된 포토레지스트(2) 위에 헥사메틸디실라제인을 160℃내지 180℃의 온도로 분무하여 부피가 증가된 새로운 포토레지스트패턴(1)을 얻었다. 새로이 얻어진 포토레지스트패턴은 표시창이 0.35㎛ 크기의 크기(5′)를 갖었다.The photoresist pattern 2 was formed on the silicon wafer substrate 3 by a conventional photolithography method. The thus formed photoresist pattern 2 had a display window between the photoresists having a size (5 ') of 0.5 mu m. Hexamethyldisilazane was sprayed on the formed photoresist 2 at a temperature of 160 ° C to 180 ° C to obtain a new photoresist pattern 1 having increased volume. The newly obtained photoresist pattern had a size (5 ') of 0.35 탆 in size.

Claims (3)

일반적인 사진식각 방법에 따라 반도체 기판상에 포토레지스트패턴을 형성한 후, 이 포토레지스트와 화학적 반응으로 포토레지스트의 분자량을 증가시켜 포토레지스트의 부피를 증가시키는 화합물로 처리하여 포토레지스트사이에 형성되는 표시창의 크기를 감소시키는 것으로 행하여짐을 특징으로 하는 미세 접촉창의 형성방법.After the photoresist pattern is formed on the semiconductor substrate according to a general photolithography method, a display window is formed between the photoresists by treating the photoresist with a compound that increases the molecular weight of the photoresist by increasing the molecular weight of the photoresist. The method of forming a micro contact window, characterized in that it is done by reducing the size of. 제1항에 있어서, 포토레지스트와 화학적 반응으로 포토레지스트의 분자량을 증가시켜 포토레지스트의 부피를 증가시키는 화합물의 처리는 실란 화합물을 160℃ 내지 180℃의 고온으로 포토레지스트에 분무하는 것으로, 행하여짐을 특징으로 하는 방법.The method of claim 1, wherein the treatment of the compound which increases the molecular weight of the photoresist by chemical reaction with the photoresist to increase the volume of the photoresist is performed by spraying the silane compound on the photoresist at a high temperature of 160 ° C to 180 ° C. How to feature. 제2항에 있어서, 상기 실란화합물이 헥사메틸디실라제인(HMDS), 테트라메틸디실라제인(TMDS), 트리메틸실릴린디에틸아민(TMSDEA), 디메틸실릴디에틸아민 (HMS DEA), 헥사메틸사이클로트리실라제인(HMCTS)임을 특징으로 하는 방법.The silane compound according to claim 2, wherein the silane compound is hexamethyldisilazane (HMDS), tetramethyldisilazane (TMDS), trimethylsilyldiethylamine (TMSDEA), dimethylsilyldiethylamine (HMS DEA), hexamethylcyclo Trisilazane (HMCTS).
KR1019920014860A 1992-08-18 1992-08-18 Fine contact hole forming method of semiconductor device KR960000369B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920014860A KR960000369B1 (en) 1992-08-18 1992-08-18 Fine contact hole forming method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920014860A KR960000369B1 (en) 1992-08-18 1992-08-18 Fine contact hole forming method of semiconductor device

Publications (2)

Publication Number Publication Date
KR940004835A KR940004835A (en) 1994-03-16
KR960000369B1 true KR960000369B1 (en) 1996-01-05

Family

ID=19338142

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920014860A KR960000369B1 (en) 1992-08-18 1992-08-18 Fine contact hole forming method of semiconductor device

Country Status (1)

Country Link
KR (1) KR960000369B1 (en)

Also Published As

Publication number Publication date
KR940004835A (en) 1994-03-16

Similar Documents

Publication Publication Date Title
JPH0777809A (en) Method for formation of pattern making use of silylation
US20040009436A1 (en) Methods for forming resist pattern and fabricating semiconductor device using Si-containing water-soluble polymer
KR20040015955A (en) Method for forming fine patterns of semiconductor device using vapor phase silylation
KR950034481A (en) Dry microlithography processing
JPH0588375A (en) Formation of resist pattern
KR950004908B1 (en) Photoresist compositions and patterning method of using them
KR100310257B1 (en) Method of forming minute pattern in semiconductor device
KR0182851B1 (en) Formation of resist pattern
KR960000369B1 (en) Fine contact hole forming method of semiconductor device
EP0889367A1 (en) Method for forming a photoresist pattern
CN1846297A (en) A method of forming a teos cap layer at low temperature and reduced deposition rate
JP5573306B2 (en) Photomask blank manufacturing method
US6190837B1 (en) Method for forming photoresist film pattern
KR100200685B1 (en) Method of forming fine pattern with photo-lithography
US20070048988A1 (en) Method for manufacturing semiconductor device using polymer
KR100545185B1 (en) Method for fabricating fine contact hole
US20100105207A1 (en) Method for forming fine pattern of semiconductor device
JP3416973B2 (en) Method of manufacturing phase shift mask
JPH10333341A (en) Forming method of resist pattern and production of semiconductor device
US7595145B2 (en) Method of forming pattern of semiconductor device
KR100545172B1 (en) A photo-lithography method of a semiconductor device
KR100390991B1 (en) Forming method for photoresist pattern of semiconductor device
KR100277573B1 (en) Fine pattern formation method
KR0172522B1 (en) Method for forming resist pattern for for micropattern
KR950005263B1 (en) Fine pattern forming method of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20011207

Year of fee payment: 7

LAPS Lapse due to unpaid annual fee