KR950026176A - Digital Luminance Crosstalk Cancellation Circuit - Google Patents
Digital Luminance Crosstalk Cancellation Circuit Download PDFInfo
- Publication number
- KR950026176A KR950026176A KR1019940003253A KR19940003253A KR950026176A KR 950026176 A KR950026176 A KR 950026176A KR 1019940003253 A KR1019940003253 A KR 1019940003253A KR 19940003253 A KR19940003253 A KR 19940003253A KR 950026176 A KR950026176 A KR 950026176A
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- South Korea
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- output signal
- multiplication
- outputting
- delay
- signal
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- Television Signal Processing For Recording (AREA)
Abstract
영상재생장치에 있어서 재생 휘도신호의 손상을 억제하며 휘도신호의 크로스토크성분을 제거하기 위한 디지탈 휘도 디지탈 휘도 크로스토크 제거회로가 개시되고 있다. 본 발명은 영상 재생을 위한 FM복조신호를 입력받아 1/2곱셈연산하여 출력하는 곱셈수단과, 상기 곱셈수단의 곱셈연산 출력신호를 입력받아 1H시간동안 지연하여 출력하는 지연수단과, 상기 곱셈수단의 곱셈연산 출력신호과 상기 지연수단의 1H시간전 입력된 지연출력신호를 입력받으며, 상기 곱셈수단의 출력신호로부터 상기 지연수단의 출력신호를 감산하여 그 감산결과를 출력하는 제1감산수단과, 소정 크로스토크 기준레벨을 구비하며, 상기 제1감산기의 출력신호를 입력받아 상기 출력신호내에 포함된 상기 기준레벨이하의 크로스토크성분을 제가하여 출력하는 제한수단과, 상기 제한수단의 출력신호를 감산하여 그 감산결과를 출력하는 제2감산수단으로 구성된다.A digital luminance digital luminance crosstalk elimination circuit for suppressing damage of a reproduction luminance signal and removing crosstalk components of a luminance signal in a video reproducing apparatus is disclosed. According to the present invention, multiplication means for receiving an FM demodulation signal for reproducing an image and outputting the result of 1/2 multiplication, delay means for receiving and outputting the multiplication operation output signal of the multiplication means for a delay of 1H time, and the multiplication means First subtraction means for receiving a multiplication operation output signal of and a delay output signal inputted 1H time ago of the delay means, subtracting the output signal of the delay means from the output signal of the multiplication means, and outputting the subtraction result; Limiting means having a crosstalk reference level and receiving an output signal of the first subtractor to subtract and output a crosstalk component below the reference level included in the output signal, and subtracting the output signal of the limiting means; And second subtracting means for outputting the subtraction result.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 본 발명에 따른 크로스 토크 제거회로의 블록 구성도.1 is a block diagram of a crosstalk removing circuit according to the present invention.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940003253A KR950026176A (en) | 1994-02-23 | 1994-02-23 | Digital Luminance Crosstalk Cancellation Circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940003253A KR950026176A (en) | 1994-02-23 | 1994-02-23 | Digital Luminance Crosstalk Cancellation Circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR950026176A true KR950026176A (en) | 1995-09-18 |
Family
ID=66689566
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940003253A KR950026176A (en) | 1994-02-23 | 1994-02-23 | Digital Luminance Crosstalk Cancellation Circuit |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR950026176A (en) |
-
1994
- 1994-02-23 KR KR1019940003253A patent/KR950026176A/en not_active IP Right Cessation
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| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| SUBM | Submission of document of abandonment before or after decision of registration |