KR950024215A - High voltage generator circuit using fuse - Google Patents

High voltage generator circuit using fuse Download PDF

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Publication number
KR950024215A
KR950024215A KR1019940001681A KR19940001681A KR950024215A KR 950024215 A KR950024215 A KR 950024215A KR 1019940001681 A KR1019940001681 A KR 1019940001681A KR 19940001681 A KR19940001681 A KR 19940001681A KR 950024215 A KR950024215 A KR 950024215A
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KR
South Korea
Prior art keywords
high voltage
output
circuit
voltage
node
Prior art date
Application number
KR1019940001681A
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Korean (ko)
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KR960009954B1 (en
Inventor
권규완
박주원
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019940001681A priority Critical patent/KR960009954B1/en
Publication of KR950024215A publication Critical patent/KR950024215A/en
Application granted granted Critical
Publication of KR960009954B1 publication Critical patent/KR960009954B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 테스트 모드시에 이용할 패드와 패드로 인가된 높은 전압을 감지하는 고전압 감지기와 상기 고전압 감지기의 출력에 의해 인에이블되어 초기 동작을 시작하는 클럭 발생기와 상기 클럭 발생기의 출력에 의해 동작이 제어되어 출력단(Vpump)에 전하를 펍핑하는 전하 펌핑회로와 상기 전하 펌핑회로의 출력(Vpump)을 다단계로 강하시켜 출력하는 전압 분배기와 상기 전압 분배기의 출력을 입력으로 하며 입력된 신호의 전위에 따라 클럭 발생기를 적절히 제어하는 클럭 제어회로로 구성되며, 상기 고저항 퓨즈를 포함하고 있는 클럭 제어회로의 퓨즈를 필요에 따라 적절히 끊어줌으로써, 고전압 출력을 원하는 전위로 조절하는 고전압 발생회로에 관한 기술이다.According to the present invention, the operation is controlled by a high voltage detector for detecting a high voltage applied to the pad to be used in the test mode and a clock generator which is enabled by an output of the high voltage detector and starts an initial operation. And a voltage divider for dropping the output of the charge pumping circuit and a voltage divider outputting the output voltage of the charge pumping circuit in multiple stages and outputting the output of the voltage divider. A high voltage generation circuit for controlling a high voltage output to a desired potential by appropriately disconnecting a fuse of a clock control circuit including the high resistance fuse as necessary.

Description

류즈를 이용한 고전압 발생회로High voltage generation circuit using Lew's

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 고전압 발생회로를 도시한 블럭도.2 is a block diagram showing a high voltage generating circuit of the present invention.

제3도는 본 발명에 의한 전압 분배기의 실시예를 도시한 회로도.3 is a circuit diagram showing an embodiment of a voltage divider according to the present invention.

Claims (3)

반도체 소자의 고전압 발생회로에 있어서, 고전압 출력단의 전위를 원하는 레벨로 조정하기 위하여, 소자의 내부회로가 동작하지 않는 고전압 테스트 모드시에 소자 외부로부터 인가된 높은 전압을 입력으로 하여 인에이블 되는 고전압 감지기와, 상기 고전압 감지기의 출력에 의해 초기 동작을 시작하는 클럭 발생기와, 상기 클럭 발생기의 출력에 의해 동작이 제어되어 고전압 출력단에 전하를 펌핑하는 전하 펌핑회로와, 상기 전하 펌핑회로의 출력을 다단계로 강하시켜 출력하는 전압 분배기와, 상기 전압 분배기로부터 출력된 다단계의 전위를 갖는 신호를 입력으로 하며 고저항 퓨즈를 사용하여 고전압 출력단의 전위를 조절할 수 있도록 구현한 클럭 제어회로를 포함하는 것을 특징으로 하는 고전압 발생회로.In a high voltage generation circuit of a semiconductor device, in order to adjust the potential of the high voltage output terminal to a desired level, a high voltage detector enabled by inputting a high voltage applied from the outside of the device in a high voltage test mode in which the internal circuit of the device does not operate. And a clock generator for starting initial operation by the output of the high voltage detector, a charge pumping circuit for controlling operation by the output of the clock generator to pump charge to a high voltage output stage, and an output of the charge pumping circuit in multiple stages. And a clock control circuit configured to input a signal having a multi-level potential outputted from the voltage divider as a drop and output the voltage divider, and to adjust the potential of the high voltage output terminal by using a high resistance fuse. High voltage generator circuit. 제1항에 있어서, 상기 전압 분배기는, 드레인과 게이트가 공통 접속되고 소오스와 벌크가 공통 접속된 다이오드 구조의 트랜지스터가 다수 개 직렬 접속되어 있으며, 첫 번째 트랜지스터의 소오스와 벌크가 공통 접속된 노드에 고전압 출력단이 연결되고, 각각의 드레인과 게이트가 공통 접속된 노드로 상기 고전압 출력단에서 각기 다른 레벨로 전압 강하된 하나 이상의 출력을 발생시키는 것을 특징으로 하는 고전압 발생회로.2. The voltage divider of claim 1, wherein the voltage divider is connected to a node in which a plurality of transistors of a diode structure having a drain and a gate are commonly connected and a source and a bulk are commonly connected, and a source and a bulk of the first transistor are commonly connected. A high voltage generation circuit comprising a high voltage output terminal connected to each other and a drain and gate connected to each other to generate one or more outputs having different voltage levels at the high voltage output terminal. 제1항에 있어서, 상기 클럭 제어회로는, 상기 전압 분배기의 출력을 반전시키는 반전 게이트와, 제1노드와 접지전압 사이에 접속된 저항 성분과, 전원전압과 상기 제1노드 사이에 접속된 고저항 퓨즈와, 상기 제1노드와 반전 게이트의 출력인 제2노드를 입력으로 하는 노아 게이트로 구성된 회로를 상기 전압 분배기의 출력수 만큼 포함하고, 상기 전압 분배기의 출력수 만큼 구현된 회로의 각각의 출력을 조합하여 상기 클럭 발생기를 제어하는 하나의 신호로 출력하는 조합회로로 구현된 것을 특징으로 하는 고전압 발생회로.The clock control circuit of claim 1, wherein the clock control circuit comprises: an inverted gate for inverting the output of the voltage divider, a resistor component connected between a first node and a ground voltage, and a high voltage connected between a power supply voltage and the first node. A circuit comprising a resistor fuse and a noah gate for inputting the first node and a second node which is an output of the inverting gate as the number of outputs of the voltage divider, and each circuit of the circuit implemented as the number of outputs of the voltage divider. A high voltage generation circuit comprising a combination circuit for combining the output to output a signal for controlling the clock generator. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940001681A 1994-01-31 1994-01-31 High voltage generating circuit using fuse KR960009954B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940001681A KR960009954B1 (en) 1994-01-31 1994-01-31 High voltage generating circuit using fuse

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940001681A KR960009954B1 (en) 1994-01-31 1994-01-31 High voltage generating circuit using fuse

Publications (2)

Publication Number Publication Date
KR950024215A true KR950024215A (en) 1995-08-21
KR960009954B1 KR960009954B1 (en) 1996-07-25

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6060942A (en) * 1997-04-22 2000-05-09 Samsung Electronics, Co., Ltd. Voltage boosting power supply circuit of memory integrated circuit and method for controlling charge amount of voltage boosting power supply

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6060942A (en) * 1997-04-22 2000-05-09 Samsung Electronics, Co., Ltd. Voltage boosting power supply circuit of memory integrated circuit and method for controlling charge amount of voltage boosting power supply

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Publication number Publication date
KR960009954B1 (en) 1996-07-25

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