KR950023093A - Channel assignment circuit for all electronic switch - Google Patents
Channel assignment circuit for all electronic switch Download PDFInfo
- Publication number
- KR950023093A KR950023093A KR1019930026888A KR930026888A KR950023093A KR 950023093 A KR950023093 A KR 950023093A KR 1019930026888 A KR1019930026888 A KR 1019930026888A KR 930026888 A KR930026888 A KR 930026888A KR 950023093 A KR950023093 A KR 950023093A
- Authority
- KR
- South Korea
- Prior art keywords
- channel
- data
- mode
- subscriber
- channel allocation
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q1/00—Details of selecting apparatus or arrangements
- H04Q1/18—Electrical details
- H04Q1/30—Signalling arrangements; Manipulation of signalling currents
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Exchange Systems With Centralized Control (AREA)
- Telephonic Communication Services (AREA)
Abstract
본 발명은 전전자 교환기의 채널(channel)할당 회로에 관한 것으로, 프로그램에 의한 기능불량을 제거하여 신뢰성을 향상시키고 비용적감이 가능한 전전자 교환기의 채널 할당 회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel assignment circuit of an all-electronic exchange. The present invention relates to a channel allocation circuit of an all-electronic exchange that can improve reliability by eliminating malfunctions caused by a program and reducing costs.
본 발명의 전전자 교환기용 채널 할당 회로는 채널 할당에 필요한 채널 할당 데이타와 제어신호를 공급하는 채널할당 제어 프로세서와, 상기 제어신호에 포함된 모드신호에 응답하여 가입자 보드의 필요한 기능 수행에 따라 선택되는 제1 내지 제5모드 신호를 발생하는 모드 선택 회로와, 상기 모드 선택 회로에 접속되어 제5모드에서 채널 할당 제어 프로세서로 가입자 고유식별 코드를 제공하기 위한 가입자 식별 코드부와, 가입자 채널로부터 수신된 가입자 훅 상태 병렬 데이타를 직렬 데이타로 변환하기 위한 제1 및 제2병렬/직렬 변환기와, 상기 제2모드에서 상기 가입자 훅 상태 직렬 데이타를 그리고 제4모드에서 가입자 채널의 SLAC로부터 데이타를 상기 채널할당 프로세서에 송신하고 상기 채널 할당 프로세서로부터의 채널 할당 데이타를 수신하기 위한 데이타 송/수신 제어부와, 제3모드에서 상기 데이타 송/수신 제어부로부터 수신된 채널 할당 데이타를 어드레스 신호에 따라 선택된 채널로 송신하기 위한 채널 선택 회로와, 상기 제1모드에서 상기 채널할당 프로세서로부터 수신된 데이타를 다시 재송출하기 위한 데이타 루프백 회로와, PCM신호를 각 채널로 인터페이스하기 위한 PCM신호 인터페이스부로 구성된다.The channel allocating circuit for an electronic switching system of the present invention selects a channel allocation control processor for supplying channel allocation data and control signals necessary for channel allocation, and performing a necessary function of a subscriber board in response to a mode signal included in the control signal. A mode selection circuit for generating first to fifth mode signals, a subscriber identification code section connected to the mode selection circuit to provide a subscriber identification code to a channel allocation control processor in a fifth mode, and received from a subscriber channel First and second parallel / serial converters for converting the subscriber hook state parallel data into serial data, and the subscriber hook state serial data in the second mode and data from the SLAC of the subscriber channel in the fourth mode. Transmit to the allocation processor and receive channel allocation data from the channel allocation processor. A data transmission / reception control unit for transmitting data, a channel selection circuit for transmitting channel allocation data received from the data transmission / reception control unit in a third mode to a channel selected according to an address signal, and a channel assignment processor in the first mode. And a data loopback circuit for retransmitting the received data, and a PCM signal interface unit for interfacing the PCM signal to each channel.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명의 바람직한 일실시예에 따른 전전자 교환기용 채널할당 회로의 블록도,2 is a block diagram of a channel assignment circuit for an all-electronic exchange according to a preferred embodiment of the present invention;
제3도는 제2도의 채널할당 회로의 상세블록도이다.3 is a detailed block diagram of the channel assignment circuit of FIG.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930026888A KR0153012B1 (en) | 1993-12-08 | 1993-12-08 | Channel allotment circuit for the full electronic switching system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930026888A KR0153012B1 (en) | 1993-12-08 | 1993-12-08 | Channel allotment circuit for the full electronic switching system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950023093A true KR950023093A (en) | 1995-07-28 |
| KR0153012B1 KR0153012B1 (en) | 1998-11-16 |
Family
ID=19370254
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930026888A KR0153012B1 (en) | 1993-12-08 | 1993-12-08 | Channel allotment circuit for the full electronic switching system |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0153012B1 (en) |
-
1993
- 1993-12-08 KR KR1019930026888A patent/KR0153012B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR0153012B1 (en) | 1998-11-16 |
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| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20020329 Year of fee payment: 5 |
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| LAPS | Lapse due to unpaid annual fee |