KR950022106A

KR950022106A - System Stabilization Reset Circuit

Info

Publication number: KR950022106A
Application number: KR1019930030555A
Authority: KR
Inventors: 이승영
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1993-12-29
Filing date: 1993-12-29
Publication date: 1995-07-26

Abstract

본 발명은 시스템 안정화 리세트회로에 관한 것으로 파워 온 리세트회로 뿐만 아니라 시스템이 불안정한 동작중이나 시스템에서 리세트신호를 요구할 때 리세트-요구-리세트신호를 동작함으로써 시스템을 초기상태나 동작중에도 안정적으로 동작할 수 있도록 한 것에 관한 것이다.The present invention relates to a system stabilization reset circuit, which operates a reset-request-reset signal when the system requires an reset signal as well as a power-on reset circuit. It's about making things work.

종래의 리세트회로는 캐패시터(12)가 완전하게 방전하게 방전되어진 상태에서는 정확하게 리세트신호가 출력되나 완전하게 방전되지 않으면 리세트 구간이 좁아질 우려가 있으며 또한 전원이 순간적으로 '오프'되었다가 '온'되었을때 잔여 캐패시터에 차아지가 그대로 남아 있게 되며 한편으로 파워온-리세트회로만으로 구성되어 있는 회로에서는 시스템이 불안정한 동작중이거나 시스템에서 리세트신호를 요구할때 시스템적으로 리세트신호로 동작할 수 없으므로 시스템을 초기상태나 동작중에 안정적으로 시스템을 동작할 수 없는 문제점을 가지고 있는 문제점이 있었다.In the conventional reset circuit, the reset signal is output correctly when the capacitor 12 is completely discharged, but there is a fear that the reset section may be narrowed if the capacitor 12 is not completely discharged. When it is 'on', the charge remains in the remaining capacitors. On the other hand, the circuit consisting of only the power-on-reset circuit is used as a system reset signal when the system is unstable or when the system requires a reset signal. There was a problem that the system can not operate stably in the initial state or during operation because it can not operate.

본 발명은 파워온-리세트뿐만 아니라 시스템이 불안정한 동작중에 시스템에서 리세트신호를 요구할때 리세트 신호를 동작시킬 수 있음을 특징으로 하여 시스템이 초기상태나 동작중에도 안정적으로 동작할 수 있도록 하여 사용할 수 있다.The present invention is characterized in that the reset signal can be operated when the system requires the reset signal during the unstable operation as well as the power-on-reset so that the system can operate stably even during the initial state or operation. Can be.

Description

System Stabilization Reset Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 의한 시스템 안정화 리세트회로의 구성도,3 is a configuration diagram of a system stabilization reset circuit according to the present invention;

제4도는 본 발명에 의한 시스템 안정화 리세트회로의 동작을 나타내는 타이밍도이다.4 is a timing diagram showing the operation of the system stabilization reset circuit according to the present invention.

Claims

A switching 36 for applying power; A resistor 37 for causing the input signal to time-delay by a time constant T1, and a capacitor 38; A two-stage Schmitt trigger (39, 40) for preventing backlash generation of the signal input through the resistor (37) and the capacitor (38) and generating a power-on-reset signal 'high'; A switch 30 intentionally generating a reset-request signal; Each board A, B, C, D for inputting a plurality of reset-request signals; A switch 31 and a buffer 31 for connecting the reset-request signals from the boards A, B, C, and D with the AND gate 32; An AND gate 32 which "ends" the signal output from the buffer 31 to the edge detection circuit 33; An edge detection circuit 33 which receives the output signal of the AND gate 32 and accepts the rising-edge signal and outputs a reset-request-reset signal; A low time adjusting circuit 34 for adjusting the rising-edge signal by a long time by the time constant T2; When the power-on-reset signal input through the terminal G is 'low' When the power-on-reset signal input through the terminal F is output as a reset signal and the power-on-reset signal is 'high' And a selector 35 for outputting the reset signal using the reset-request-reset signal input through the terminal E as a selection signal.

※ Note: The disclosure is based on the initial application.