KR950022066A - FIR filter circuit using QPSK and OQPSK modulation - Google Patents

Abstract

The present invention relates to a circuit of a FIR filter that stores T taps of QPSK modulation method and OQPSK modulation method, 1: N interpolation ratio, B coefficient bit number, and A output bit number. A new FIR filter input method using multiplexed FIR filter inputs reduces the FIR filter of two channels into one, and integrates a new configuration factor ROM addressing method in which the selected coefficient group and all possible filter input data are premultiplied, accumulated and stored. The purpose is to minimize the circuit configuration and to minimize the power consumption and chip size.

Two T / N bit shift registers 23 and 24 and I-channel data and Q-channel data for respectively inputting QPSK modulation scheme I-data and Q-data by CK (2N) B to achieve the above object. Two T / 2N bit MUXs (25, 26) which are multiplexed by CK2 and inputted to the address of the integration coefficient ROM, and two integration coefficient ROMs (27) in which subgroup N integration results N * 2 ^{T / 2N} are input and stored. And the output of the (B + 1) bit adder 29 and the (B + 1) bit adder 29, which add the output of the ROM, are inputted and stored by the CK1B, and are modulated for the CDMA base station. It consists of one clock divider CK1 which is a system clock of a part. Another OQPSK modulation scheme is an in-phase T / N bit shift register 23 for shifting I-data to CK (2N) and an in-phase T / N for shifting CK (2N) to half-sample delay for Q-data. Bit shift register 23 and antiphase T / N bit shift register 34 for shifting Q-data to CK (2N) for half-sample delay, and two log ₂ N + T / 2N bit MUX (35,36) And two integration coefficients ROM 27 and 28, a B + 1 bit adder 29, an A bit register 30, and one clock divider.

Description

F-IR filter circuit using QPSK and OQPSK modulation method

Since this is an open matter, no full text was included.

1 is a block diagram showing portions of QPSK and OQPSK modulators.

2 is a block diagram showing the function of a conventional basic 1: 4 interpolation FIR filter.

Figure 3 is a block diagram showing a 1: N interpolation FIR filter of the QPSK modulation method according to the present invention.

Figure 4 is a block diagram showing a 1: N interpolation FIR filter of the QPSK modulation method according to the present invention.

5 is a block diagram showing a 1: 4 interpolation FlR filter of the OQPSK modulation scheme according to the present invention.

6 is a block diagram showing a 1: N interpolation FIR filter of the OQPSK modulation scheme according to the present invention.

FIG. 7 is a block diagram showing addresses and stored data of ROM_1 and ROM_2 according to FIG. 3 and FIG.

8 is a block diagram showing addresses of ROM_1 and ROM_2 and stored data according to FIGS. 4 and 6;

9 is an operation waveform diagram of a 1: 4 interpolation FIR filter of QPSK modulation scheme according to FIG.

10 is an operation waveform diagram of a 1: 4 interpolation FIR filter of the OQPSK modulation method according to FIG.

Claims (3)

In a circuit of a FIR filter having a T tap 1: N interpolation ratio, a B coefficient bit, and an A output bit number using a QPSK modulation method for a CDMA base station, an I-channel PN column 1 and a Q-channel PN column (2). Two T / N bit shift registers 23 and 24 for inputting I_data and Q-data spread by CK (2N) B, respectively, and I-channel data and Q_channel data by CK2. Two T / 2N bit MUXs (25, 26) multiplexed and inputted into the address of the integration coefficient ROM, and two integration coefficient ROMs (27, 28) in which N ^* 2 ^{T / 2N} of the subgroup N integration results are input and stored. ), An (B + 1) bit adder 29 that adds the output of the ROM, an A bit register 30 to which an output of the (B + l) bit adder 29 is input and stored by CK1B, and And a clock divider (CK1) which is a system clock of the modulation portion for the CDMA base station. 2. The two T / N bit shift registers 23 and 24 are divided into in-phase T / N bit shift registers 23 and antiphase T / N bit shift registers 24, respectively. A FIR filter circuit according to the QPSK modulation method, characterized in that a data bit first inputted into the upper T / 2N bit is referred to as a lower T / 2N bit. In a FIR filter circuit having a T tap 1: N interpolation ratio, a B coefficient bit, and an A output bit number according to the OQPSK modulation method for CDAM, the I-channel input I-data is shifted to CK (2N) B. The phase T / N bit shift register 23 and the antiphase T / N bit shift register 34 for shifting the CK (2N) to half-sample delay of the Q-channel input Q-data, and log ₂ N bits Two log ₂ N + T / 2N bit MUXs (35,36) for adding and addressing the address input of the ROM, two integration coefficients (27,28), and (B + l) for adding the output of the ROM. Bit adder 29, the A bit register 30 into which the output of the (B + l) bit adder 29 is inputted and stored by CK1B, and one clock that is a system clock of the modulation portion for the CDMA base station. An FIR filter circuit based on an OQPSK modulation method comprising a divider (CK1). ※ Note: The disclosure is based on the initial application.