KR950021932A - Fuserom Circuit - Google Patents

Fuserom Circuit Download PDF

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Publication number
KR950021932A
KR950021932A KR1019930032043A KR930032043A KR950021932A KR 950021932 A KR950021932 A KR 950021932A KR 1019930032043 A KR1019930032043 A KR 1019930032043A KR 930032043 A KR930032043 A KR 930032043A KR 950021932 A KR950021932 A KR 950021932A
Authority
KR
South Korea
Prior art keywords
fuse
transistor
pmos transistor
circuit
blown
Prior art date
Application number
KR1019930032043A
Other languages
Korean (ko)
Other versions
KR970004361B1 (en
Inventor
주양성
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019930032043A priority Critical patent/KR970004361B1/en
Publication of KR950021932A publication Critical patent/KR950021932A/en
Application granted granted Critical
Publication of KR970004361B1 publication Critical patent/KR970004361B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/027—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in fuses

Abstract

본 발명은 퓨즈롬 회로에 관한 것으로, 종래 퓨즈롬 회로는 퓨즈가 끊어질 경우 외부에서 파워가 안가되는 동안 노드 N1의 상태가 불안정하고 그 퓨즈의 저항성분이 존재하면, 턴-온된 엔모스트랜지스터에 의해 전원단자(Vcc)에서 접지단자(Vss)로 리크전류가 흘러 전력소모가 발생한다. 또한, 퓨즈가 끊어진 후 테스트를 실시하여 그 테스트 결과 퓨즈롬을 디스에이블(disable)시킬 경우 불가능하게 되는 문제점이 있었다. 본 발명은 이러한 문제점을 해결하기 위하여 퓨즈의 상태를 샘플링하여 출력으로 나타내고, 정상동작시 퓨즈가 끊어지더라도 샘플링한 값을 그대로 유지토록 하는 퓨즈를 회로를 창안한 것이다.The present invention relates to a fuse-rom circuit. In the conventional fuse-rom circuit, when the fuse is blown, if the state of the node N1 is unstable while the power is not supplied from the outside and the resistance of the fuse is present, the turned-on transistor is turned on. The leakage current flows from the power supply terminal (Vcc) to the ground terminal (Vss) to generate power consumption. In addition, when the fuse is blown and the test is performed, the test result has a problem that it becomes impossible to disable the fuse. In order to solve this problem, the present invention is designed to output a circuit by sampling the state of the fuse, and to maintain the sampled value even when the fuse is blown during normal operation.

Description

퓨즈롬 회로Fuserom Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래의 퓨즈롬 회로도,1 is a conventional fuse ROM circuit diagram,

제2도는 본 발명의 퓨즈롬 회로도,2 is a fuse ROM circuit diagram of the present invention;

제3도는 제2도에 대한 다른 실시 회로도,3 is another implementation circuit diagram for FIG.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

Q10,Q14: 엔모스트랜지스터Q11,Q12,Q13: 피모스트랜지스터Q 10 , Q 14 : NMOS transistor Q 11 , Q 12 , Q 13 : PMOS transistor

I10: 인버터I 10 : Inverter

Claims (2)

제어신호()()가 게이트에 각기 접속된 엔모스트랜지스터(Q10)와 피모스트랜지스터(Q11)의 드레인을 공통접속(N2)하여 그 접속점(N2)을 상기 제어신호()가 게이트에 접속되는 피모스트랜지스터(Q12)의 드레인에 접속하고, 상기 피모스트랜지스터(Q11)의 소오스를 퓨즈(FS1)를 통해 전원단자(Vcc)에 접속함과 아울러 상기 엔모스트랜지스터(Q10)의 소오스를 퓨즈(FS2)를 통해 접지시키고, 상기 엔모스트랜지스터(Q10)와 피모스트랜지스터(Q11)(Q12)의 공통 드레인 접속점(N2)을 인버터(I10)를 통해 출력단자(out)에 접속하며, 상기 출력단자(out)를 피모스트랜지스터(Q13)와 엔모스트랜지스터(Q14)의 게이트에 접속하고, 상기 피모스트랜지스터(Q13)와 엔모스트랜지스터(Q14)의 드레인을 공통 접속하고, 그 접속점을 상기 인버터(I10)의 입력측에 접속하여 구성한 것을 특징으로 하는 퓨즈롬 회로.Control signal ( ) ( ) Are commonly connected to the drains of the NMOS transistor Q 10 and the PMOS transistor Q 11 respectively connected to the gate thereof, and the connection point N2 is connected to the control signal (N2). ) Is connected to the drain of the PMOS transistor Q 12 connected to the gate, the source of the PMOS transistor Q 11 is connected to the power supply terminal Vcc through the fuse FS1, and the NMOS transistor The source of Q 10 is grounded through the fuse FS2, and the common drain connection point N2 of the MOS transistor Q 10 and the PMOS transistor Q 11 and Q 12 is connected to the inverter I 10 . through connection to a gate of, and connected to the output terminal (out), the output terminal (out) a PMOS transistor (Q 13) and NMOS transistor (Q 14), and the PMOS transistor (Q 13) and the NMOS transistors A fuse ROM circuit comprising a common connection of a drain of (Q 14 ) and a connection point connected to an input side of the inverter (I 10 ). 제1항에 있어서, 엔모스트랜지스터(Q10)와 피모스트랜지스터(Q11)를 바꾸어 구성한 것을 특징으로 하는 퓨즈롬 회로.2. The fuse ROM circuit according to claim 1, wherein the MOS transistor (Q 10 ) and the PMOS transistor (Q 11 ) are replaced with each other. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930032043A 1993-12-31 1993-12-31 Fuse rom circuit KR970004361B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930032043A KR970004361B1 (en) 1993-12-31 1993-12-31 Fuse rom circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930032043A KR970004361B1 (en) 1993-12-31 1993-12-31 Fuse rom circuit

Publications (2)

Publication Number Publication Date
KR950021932A true KR950021932A (en) 1995-07-26
KR970004361B1 KR970004361B1 (en) 1997-03-27

Family

ID=19374970

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930032043A KR970004361B1 (en) 1993-12-31 1993-12-31 Fuse rom circuit

Country Status (1)

Country Link
KR (1) KR970004361B1 (en)

Also Published As

Publication number Publication date
KR970004361B1 (en) 1997-03-27

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