KR950020231A - Dual write method and device for processor board redundancy - Google Patents

Abstract

Disclosed are a dual writing apparatus and method for processor board duplication of an exchange system that can reduce the number of system boards, as well as simplify hardware debugging. Such an apparatus and method is provided with a device structure that prevents the performance degradation of the main processor by installing a redundant bus separately from the MPS bus of the main processor module and performing dual writes through the redundant bus. If the data to be provided is a dual write, outputting a dual write start signal through a buffer after latching the address and data; checking whether the dual write is completed on the other side when the dual write on the own side is completed; Has an operation of performing another operation when the operation is not completed, and the other side accepts an address and data from the buffer and generates a memory request signal in response to the duplication write start signal, and after completion of the memory write operation. Generating and transmitting a completion signal.

Description

Dual write method and device for processor board redundancy

Since this is an open matter, no full text was included.

1 is a redundant structure diagram of a processor board according to the present invention;

2 is a block diagram of a dual write apparatus of the present invention;

3 and 4 are dual write control flow diagrams of an operation side and a standby side according to an embodiment of the present invention.

Claims (3)

A dual write device of an all-electronic switching system has a structure in which a redundant bus is provided separately from a bus of a dual main processor of the switched system and a dual write is performed through the redundant bus to prevent a decrease in the performance of the main processor. Device characterized in that. An apparatus for processor board duplication of an electronic switching system, comprising: a processor for controlling all operations for call processing; and a control signal for dual writing or internal memory access by decoding an address signal provided from the processor; An address decoder, a redundancy control unit which generates a dual write start control signal in response to the control signal for dual writing, and cuts off the start control signal in response to a dual write completion signal transmitted from a counterpart; And a redundancy buffer for transmitting and receiving an address and data from the processor in response to the redundancy buffer, and a detector for detecting a timeout of the dual write completion signal. A method for dualizing a processor board of an electronic switching system, the method comprising: at an operation side, if data provided from a processor is dual write, latching an address and data and outputting a dual write start signal through a buffer; Checking whether the dual write is completed on the other end when the dual write is completed, and performing another operation when the write on the other side is incomplete, and storing the address and data from the buffer in response to the dual write start signal. Generating a memory request signal and generating and transmitting a completion signal after completion of the memory write operation. ※ Note: The disclosure is based on the initial application.