KR950016336A - Data Slicing Value Correction Circuit of Multiple Character Receiver - Google Patents
Data Slicing Value Correction Circuit of Multiple Character Receiver Download PDFInfo
- Publication number
- KR950016336A KR950016336A KR1019930026159A KR930026159A KR950016336A KR 950016336 A KR950016336 A KR 950016336A KR 1019930026159 A KR1019930026159 A KR 1019930026159A KR 930026159 A KR930026159 A KR 930026159A KR 950016336 A KR950016336 A KR 950016336A
- Authority
- KR
- South Korea
- Prior art keywords
- data
- slicing value
- signal
- error
- value
- Prior art date
Links
Landscapes
- Television Systems (AREA)
Abstract
텔레비젼신호의 수직귀선기간 중에 전송되는 디지탈 데이타를 수신하는 문자다중수신기에 있어서, 수신신호의 에러발생상태에 따라 유효한 데이타 판별의 기준이 되는 데이타 슬라이싱값을 제시하는 데이타 슬라이싱값 보정회로에 관한 것이다.A character multiple receiver for receiving digital data transmitted during a vertical retrace period of a television signal, and a data slicing value correction circuit for presenting a data slicing value, which is a criterion for valid data discrimination, according to an error occurrence state of a received signal.
본 발명에 따른 데이타 슬라이싱값 보정회로는 텔레비젼 신호의 수직귀선기간중에 중첩되어 전송된 패킷을 수신하고 에러정정을 행하여 분리된 데이타를 출력하는 문자다중수신기에 있어서, 패킷신호의 진폭을 에러발생상태에 연동되는 슬라이싱값과 비교하여 파정정형된 디지탈신호를 출력하는 비교기와 비교기에서 출력되는 파형정형된 디지탈 신호를 입력하고 에러정정을 행하여 분리된 데이타 및 에러플랙을 출력하는 에러정정부; 그리고 수직동기신호에 동기되어 에러플랙의 발생상태를 검출하고, 이에 따라 슬라이싱값을 적용적으로 변화시키는 슬라이싱값 소정수단을 포함함을 특징으로 하는 것으로서 복조된 데이타의 에러발생률을 검출하고 이에 상응하여 수신기의 감도 즉 데이타 슬라이싱값을 적용적으로 조정함으로써 문자다중수신기의 복조효율을 제고하는 효과를 갖는다.A data slicing value correction circuit according to the present invention is a character multiplex receiver which receives packets transmitted overlapping during a vertical retrace period of a television signal, performs error correction, and outputs separated data. An error correction unit for inputting a waveform-formed digital signal output from the comparator and an error correction and outputting separated data and an error flag by comparing the interpolated slicing value with the output of the waveform-corrected digital signal; And a slicing value predetermined means for detecting an occurrence state of the error flag in synchronization with the vertical synchronization signal, and accordingly changing the slicing value accordingly. The error occurrence rate of the demodulated data is detected and correspondingly. By adjusting the sensitivity of the receiver, that is, the data slicing value, the demodulation efficiency of the multiplex receiver is improved.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 문자다중신호의 구성을 보이는 파형도이다.1 is a waveform diagram showing the configuration of a character multiplex signal.
제2도는 종래의 문자다중수신기의 구성을 보이는 블럭도이다.2 is a block diagram showing the configuration of a conventional character multiplex receiver.
제3도는 문자다중수신기의 수신신호 및 데이타 슬라이싱값의 관계를 보이는 도면이다.3 is a diagram showing the relationship between the received signal and the data slicing value of the character multiplexer.
제4도는 본 발명에 따른 데이타 슬라이싱값 보성회로의 바람직한 실시예를 도시한 블럭도이다.4 is a block diagram showing a preferred embodiment of a data slicing value compensating circuit according to the present invention.
제5도는 제4도에 도시된 장치에 있어서 계수부 및 래치부의 상세한 구성을 보이는 블럭도이다.FIG. 5 is a block diagram showing the detailed configuration of the counter and the latch unit in the apparatus shown in FIG.
제6도는 제5도에 도시된 장치의 동작을 보이는 타이밍도이다.6 is a timing diagram showing the operation of the apparatus shown in FIG.
제7도는 제4도에 도시된 장치에 있어서 전압발생부의 상세한 구성을 보이는 블럭도이다.FIG. 7 is a block diagram showing a detailed configuration of the voltage generator in the apparatus shown in FIG.
제8도는 제7도에 도시된 장치의 동작을 보이는 타이밍도이다.8 is a timing diagram showing the operation of the apparatus shown in FIG.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930026159A KR950016336A (en) | 1993-11-30 | 1993-11-30 | Data Slicing Value Correction Circuit of Multiple Character Receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930026159A KR950016336A (en) | 1993-11-30 | 1993-11-30 | Data Slicing Value Correction Circuit of Multiple Character Receiver |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR950016336A true KR950016336A (en) | 1995-06-17 |
Family
ID=66826567
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930026159A KR950016336A (en) | 1993-11-30 | 1993-11-30 | Data Slicing Value Correction Circuit of Multiple Character Receiver |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR950016336A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7911534B2 (en) | 2005-07-04 | 2011-03-22 | Samsung Electronics Co., Ltd. | Video processing apparatus, ancillary information processing apparatus and video processing method |
-
1993
- 1993-11-30 KR KR1019930026159A patent/KR950016336A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7911534B2 (en) | 2005-07-04 | 2011-03-22 | Samsung Electronics Co., Ltd. | Video processing apparatus, ancillary information processing apparatus and video processing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR960028391A (en) | Receiver for receiving digital signal in tracking and retracking section of anti-television television signal | |
| EP0630545A1 (en) | Auxiliary video data slicer | |
| JPH11509706A (en) | Synchronization of digital television | |
| RU2128888C1 (en) | Sync signal generating system for line-sweep television receivers; system for generating clock-pulse signal in line-sweep television receiver; system for generating clock signal synchronized with display unit in television equipment | |
| KR100224509B1 (en) | Process for compatible transmission of a single type additional information | |
| KR890007598A (en) | SC / H phase measuring device of composite video signal | |
| KR950016336A (en) | Data Slicing Value Correction Circuit of Multiple Character Receiver | |
| KR960003395A (en) | Detection clock generator for digital data on composite video signal and data detection device using detection clock | |
| WO1991017631A1 (en) | Method and apparatus for synchronization in a digital composite video system | |
| KR920006947B1 (en) | Sync-signal reproducing circuit for use in tv-receiver | |
| KR0147851B1 (en) | Phase locked subcarrier regenerator | |
| KR100212152B1 (en) | A data detection circuit of an air-wave broadcasting | |
| JP2542707B2 (en) | Horizontal sync pulse measurement circuit | |
| KR950703253A (en) | TV LINE AND FIELD DETECTION APPARATUS WITH GOOD NOISE IMMUNITY | |
| KR910017874A (en) | Digital Receiver for Digital Data Transmission | |
| KR950016217A (en) | Clock signal generator | |
| KR960020060A (en) | Phase Shift Correction Device of Synchronous Detector in Satellite Broadcasting Receiver System | |
| KR950002212Y1 (en) | Apparatus for separating vertical synchronizing signal | |
| KR960028172A (en) | Synchronization Signal Generator of Image Device | |
| KR970078607A (en) | Subtitle location information detection device | |
| KR970019369A (en) | Line Locked Clock Generator of TV Signal | |
| KR970017424A (en) | Sector Synchronization Signal Generation Method and Device | |
| KR970019366A (en) | Start code detection device of palplus video signal | |
| KR970078675A (en) | Color Burst Signal Positioner | |
| KR860000775A (en) | Broadcasting channel reception noise cancellation circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| WITB | Written withdrawal of application |