KR950015090B1 - Mux device of multimedia - Google Patents

Abstract

a media connecting unit for connecting media from a constant bit rate video codec, an audio codec, an ISDN terminal and a data information source; a media generating unit for supplying a media output signal to the media connecting unit and receiving a media service unit and a buffer state signal from the media connecting unit to generate an SAR-PDU; a header information buffering unit for supplying a header information setting signal and header information to the media generating unit and storing and supplying the header information on the media; a media cell multiplexing unit for inputting the header information setting signal and the header information from the header information buffering unit and the media SAR-PDU from the media generating unit, multiplexing the header and the media SAR-PDU and generating an ATM cell; and a system control unit for supplying a control signal to each unit.

Description

Multimedia multiplexer

1 is a schematic block diagram of a multimedia multiplexing apparatus according to the present invention.

2 is a block diagram of a media connection circuit according to the present invention.

3 is a block diagram of a media generation circuit according to the present invention, (a) is a block diagram of a media generation circuit for video / audio / ISDN, and (b) is a block diagram of a media generation circuit for data.

4 is a block diagram of a header information buffer circuit according to the present invention.

5 is a block diagram of a media cell multiplexing circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

11: media connection circuit 12: media generation circuit

13: header information buffer circuit 14: media cell multiplexing circuit

15: system management circuit

The present invention provides video, hi-fi audio, ISDN information, and still image, graphic, text, and other data services to users during service using ATM (asynchronous transmission method), which is the transmission method of the broadband integrated information network in CCITT, an international standard organization. The present invention relates to a multimedia multiplexing device for providing.

In general, a 53 octet ATM cell is used to provide each service in a broadband integrated telecommunication network (hereinafter referred to as B-ISDN). In order to make such an ATM cell, the user information is separated and recombined through a process of separation and reassembly of the ATM Adaptation Layer (hereinafter referred to as AAL). After converting into a data unit (Segmentation And Reassembly-Protocol Data Unit (hereinafter referred to as SAR-PDU)), virtual channel information (Vitual Path Identifier / Vitual Channel Identifier: below, VPI / There is a need for a media multiplexing device that adds a 5-octet ATM header containing information such as VCI, payload type, and cell loss priority to each SAR-PDU composed of various media, and then transmits it to the physical layer. .

In order to meet the above needs, the present invention provides a timing information sequence number, an information type, and a parity check bit in each SAR-PDU payload of 47 octets, which are user information transmitted from a fixed bit rate video codec, an audio codec, and an ISDN terminal. After combining the configured one octet SAR header with SAR-PDU payload, each SAR-PDU is formed, and in the multiplexer, ATM header with one VPI / VCI and SAR-PDU of each media are combined to form ATM cell. After transmitting to the ATM network through the physical layer, it solves the synchronization problem of each media caused by the delay in the switch and node that occurs when transmitting to the ATM cell with each VPI / VCI. The structure of the SAR sublayer transmission apparatus for video, audio and ISDN information having a fixed bit rate characteristic can be provided. (92-24194), the present invention transmits to the multiplexer in the SAR-PDU unit through the function of the SAR-PDU unit for fixed bit rate video, audio, and ISDN information, and the convergence layer layer for the data information, After combining 48 octets of SAR-PDU and ATM header, ATM cell is formed and transmitted to the physical layer, so that fixed-rate video, audio, and ISDN information and variable bit rate data information are integrated. The object of the present invention is to provide a multiplexing device.

In order to achieve the above object, the present invention provides a media access unit for performing media access from a fixed bit rate video codec, an audio codec, an ISDN terminal, and a data information source, and providing a media output signal to the media access circuit. A media generating means for receiving a status signal to generate a SAR-PDU, a header information buffering means for providing a header information setting signal and header information to the media generating means, and storing and providing header information for the media, and the header information buffering means A media cell multiplexing means for generating an ATM cell by multiplexing a header and a media SAR-PDU by receiving a header information setting signal and header information from the media generating means and a media SAR-PDU from the media generating means, and a network driving clock and an external control unit To manage the connection and provide the management signal (Mi) to each circuit part. It characterized in that it comprises a system management means.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram of a multimedia multiplexing apparatus according to the present invention, in which 11 is a media access circuit, 12 is a media generating circuit, 13 is a header information buffer circuit, 14 is a media cell multiplexing circuit, and 15 is a system management circuit. Respectively.

As shown in the figure, a system management system receives a network driving clock from the outside, transmits and receives a control signal between the external control unit and the system, and outputs a management signal Mi to perform necessary control according to the status signal Si in the system. The circuit 15 (detailed configuration has been previously filed in the application number 92-24193), each of which is received from the video codec, audio codec, ISDN terminal receiving the management signal (M1) from the system management circuit 15 A media connection circuit 11 for connecting data such as media and files stored in a computer and storing the data in units of media, and buffer status signals BVHf, BAHf, BIHf, BDHf, and BDEf from the media connection circuit 11; A media service unit is provided through a media output signal (V-5, A-5, I-5, D-1) which is notified and inputs a system clock to the media access circuit 11 to receive a media SAR-PDU. And output the status signal (S2) Receive header information required for information transmission from the system generation circuit 12 and the system management circuit 15 to the ATM network by the management signal M3, and a header information setting signal is described later with the media generation circuit 12. A header information buffer circuit 13 for transmitting the header information to the media cell multiplexing circuit 14 in accordance with the header information output signal provided from the media multiplexing circuit 14; The management signal M4 from the system management circuit 15 is received according to the status signal S4 and the system clock is received, and each media SAR-PDU and the header information buffer circuit provided from the media generation circuit 12 are received. It consists of a media cell multiplexing circuit 14 which combines the ATM header provided from (13) and then forms an ATM cell and transmits it to the physical layer.

2 is a detailed block diagram of a media access circuit according to the present invention, where 20 is a media buffer, 21 is an image information input circuit, 22 is an audio information input circuit, 23 is an ISDN information input circuit, 24 is a data input circuit, 25 denotes an image information buffer, 26 denotes an audio information buffer, 27 denotes an ISDN information buffer, 28 denotes a data buffer, and 29 denotes an input circuit section.

As shown in the figure, the media connection circuit inputs an impedance matching image information input circuit 21 by inputting NRZ image information, an audio information input circuit 22 which inputs impedance matching by inputting NRZ audio information, and ISDN information. The ISDN information input circuit 23 for impedance matching, the data input circuit 24 for inputting impedance, and the impedance matched NRZ image information through the image information input circuit 21, and generating the media. An image information buffer 25 for inputting an image output signal V-5 from the circuit 12 to output an image service unit and a buffer status signal BVHf, and an impedance matched through the audio information input circuit 22. An audio information buffer 26 for inputting NRZ audio information and inputting an audio output signal A-5 from the media generating circuit 12 to output an audio service unit and a buffer status signal BAHf; ISDN information input for inputting impedance-matched ISDN information through the output circuit 23 and inputting the ISDN output signal I-5 from the media generating circuit 12 to output the ISDN service unit and the buffer status signal BIHf. Impedance-matched data is input through the circuit 27 and the data input circuit 24, and a data output signal D-1 is input from the media generating circuit 12 to supply the data service unit and the buffer status signal BDHf. , A data buffer 28 for outputting BDEf).

A description of the above configuration is added as follows.

The image information buffer 25 is driven and switched in accordance with the M1V signal of the system management circuit 15 of FIG. 1, and notifies the media generation circuit 12 of FIG. According to the V-5 signal of the circuit 12, a 47-octet video service unit is transmitted to the media generating circuit 12 of FIG.

The NRZ audio information and the audio input clock transmitted from the audio codec are stored in the audio information buffer 26 after impedance matching in the audio information input circuit 22. The audio information buffer 26 is driven and switched in accordance with the M1A signal of the system management circuit 15 of FIG. 1, and notifies the first FIG. 1 media generating circuit 12 of the buffer status signal BAHf. The 47-octet audio service unit is transmitted to the media generating circuit 12 in accordance with the A-5 signal of the generating circuit 12.

The ISDN information buffer 27 transmitted from the ISDN terminal is driven and switched according to the system management circuit 15 M1I signal of FIG. 1, and notifies the media generation circuit 12 of FIG. 1 of the buffer status signal BIHf. A 47-octet ISDN service unit is transmitted to the media generation circuit 12 in accordance with the I-5 signal of the media generation circuit 12.

Data and a data input clock transmitted from a data information source such as a computer hard disk are stored in the data buffer 28 via the data input circuit 24. It is stored in the data buffer 28. The data buffer 28 is driven and switched according to the M1D signal of the system management circuit 15 of FIG. 1, and notifies the media generation circuit 12 of the buffer status signal BDHF. The data service unit is transmitted to the media generating circuit 12 according to the D-1 signal of the "

3 is a detailed block diagram of a media generating circuit, (a) is a block diagram of a media generating circuit for video / audio / ISDN information, and (b) is a detailed block diagram of a media generating circuit for data information.

In the drawing, reference numeral 120 denotes a media unit generation unit, 121 a timing information generation circuit, 122 a counter circuit, 123 a decoding circuit, 124 an output signal control circuit, 125 a SAR header generation circuit, 126 a register, 127 a multiplexing circuit, 128 is an output alignment circuit, 130 is a data unit generation unit, 131 is a counter circuit, 132 is a decoding circuit, 133 is an output signal control circuit, 134 is a CRC generation circuit, 135 is an information length counter circuit, 136 is a redundant data generation circuit, 137 multiple circuits and 138 denote output alignment circuits, respectively.

Counter circuit 122 for driving a counter by receiving buffer status signals BVHf, BAHf, and BIHf from the media connection circuit 2 for generating SAR-PDUs for fixed bit rate video, audio, and ISDN information. A decoding circuit 123 for decoding the output of the 122, an output signal control circuit 124 for generating a necessary output control signal in accordance with the decoding signal from the decoding circuit 123, and the media connection circuit 11; Timing information generation circuit 121 and timing information generation circuit 121 for generating timing information by receiving input and network clocks of video, audio and ISDN information transmitted, and output signals from the output signal control circuit 124. SAR header generation circuit 125 which receives the timing information from the output signal and the output signal from the output signal control circuit 124 and generates a SAR header, and receives the output signal from the output signal control circuit 124. A register 126 for outputting the SAR header from the SAR header generation circuit 122, an output signal SAR header from the register 126 and a 47 octet media service unit from the media connection circuit 11 are multiplexed. A multiplexing circuit 127 for generating a SAR-PDU, and an output sorting circuit 128 for receiving an output signal from the output signal control circuit 124 and outputting the SAR-PDU from the multiplexing circuit 127; A media generating circuit for video / audio / ISDN information and a buffer status signal (BDHf) from the media access circuit (11) for generating a SAR-PDU for variable bit rate data information and receiving the header information buffer circuit (13). In response to the header information setting signal from the counter circuit 131 for driving the counter, the decoding circuit 132 for decoding the counter output of the counter circuit 131, according to the decoding signal of the decoding circuit 132 An output signal control circuit 133 for generating a required output control signal Ds, output signals D-2 and D-4 from the output signal control circuit 133, and received from the media connection circuit 11; CRC generation circuit 134 for generating 32-bit CRC for the transmitted information, and output signals D-1 and D-3 from the output signal control circuit 133 and receive from the media connection circuit 11. An information length counter circuit 135 for counting the output signal BDE data of the output signal and outputting the data length information, and receiving the output signal D-1 from the output signal control circuit 133 and receiving the media length connection circuit 11. A redundancy data generation circuit 136 for receiving the output signal BDEf from < RTI ID = 0.0 >), < / RTI > -5) from the media connection circuit 11 A multiplexing circuit for multiplexing the other service unit, excess data from the redundant data generation circuit 136, data length information from the information length counter circuit 135, and four octets of CRC from the CRC generation circuit 134 ( 137) an output alignment circuit 138 that receives the output signal D-6 from the output signal control circuit 133, receives the multiplexed output signal from the multiplexing circuit 137, and transmits the output signal in the SAR-PDU unit. And a media generating circuit for data.

A detailed description of the above configuration is added.

First, the media generation circuit for video / audio / ISDN information functions to generate a SAR-PDU for video information, audio information, and ISDN information.

They generate SAR-PDUs according to the Vs, As, and Is signals provided from the media unit generation unit 120, and each of them is controlled by the control signals M2V, M2A, M2I from the system management circuit 15 of FIG. Manage and transfer the generation circuits of the media. First, a process of generating a SAR-PDU for image information is described. The process of generating a SAR-PDU of audio and ISDN information is the same.

According to the management signal M2V, the timing information generation circuit 121, the counter circuit 122, the decoding circuit 123, the output signal control circuit 124, the SAR header generation circuit 125, the register 126, and the multiplexing circuit 127 ), The output alignment circuit 128 is driven and switched.

The timing information generation circuit 121 receives an image input clock and a network clock transmitted from the media connection circuit 11 of FIG. 1, generates timing information necessary for restoring service information at the receiving end, and generates a media unit generation unit ( The 4-bit timing information is transmitted to the SAR header generation circuit 125 according to the V-1 signal of the output signal control circuit 124 of 120. The counter circuit 122 of the media unit generating unit 120 notifies the header information setting signal transmitted from the header information buffer circuit 13 of the buffer status signal BVHf transmitted from the media connection circuit 11 of FIG. When the counter information is output to the decoding circuit 123, the decoding circuit 123 transmits a decoding signal for generating a SAR-PDU to the output signal control circuit 124, and the output signal control circuit 124 is a logic circuit. And a flip-flop to output the overall output control signal (Vs) necessary for generating the SAR-PDU, the media connection circuit 11, the timing information generation circuit 121, the SAR header generation circuit 125, and the register 126 of FIG. ), The multiplexing circuit 127, and the output alignment circuit 128. The SAR header generation circuit 125 for generating a SAR header composed of one octet, such as one bit of timing information bits, three bit sequence number bits, three bits of information type bits, and one bit of parity bits, is a timing information generation circuit ( 4) Timing information of 4 bits transmitted from 121) is used to generate the sequence number of the SAR header to Modular-8, and each bit is 1 bit for each sequence number "1", "3", "5", and "7". After inserting it into the VPI / VCI and adding the information type to distinguish the video, audio, and ISDN information to be transmitted according to the same VPI / VCI, calculate the 1-bit even parity bit, generate SAR header, and add it to the V-2 signal. Accordingly, transfer to register 126. The register 126 multiplexes 47 octets of the media service unit transmitted from the media connection circuit 11 of FIG. 1 according to the SAR header and the V-5 signal according to the V-3 signal, and transmits it to the output alignment circuit 128. do. The output sorting circuit 128 transmits the media SAR-PDU transmitted from the multiplexing circuit 127 to the media cell multiplexing circuit 14 of FIG. 1 according to the V-6 signal.

The media generating circuit for data functions to generate a SAR-PDU for the data information.

The counter circuit 131, the decoding circuit 132, the output signal control circuit 138, the inking data generation circuit 136, and the information length counter circuit in accordance with the management signal M2D of the system management circuit 15 of FIG. 1. Reference numeral 135, the CRC generation circuit 134, the multiplexing circuit 137, and the output alignment circuit 138 are driven and switched.

The counter circuit 131 of the data unit generation unit 130 notifies the buffer status signal BDHf provided from the media connection circuit 11 of FIG. 1 and the header information setting signal transmitted from the header information buffer circuit 13. If so, the counter circuit 131 is driven to output counter information to the decoding circuit 132, and the decoding circuit 132 transmits the decoding signal for generating the SAR-PDU to the output signal control circuit 133, and the logic The output signal control circuit 133 composed of a circuit and a flip-flop transmits all the output control signals Ds necessary for generating the SAR-PDU, the media connection circuit 11, the surplus data generation circuit 136, and the information length counter of FIG. The circuit 135 is supplied to the CRC generation circuit 136, the multiplexing circuit 137, and the output alignment circuit 138.

The output signal control signal 133 of the data unit generation unit 130 receives the data service unit in units of 48 octets from the media connection circuit 11 of FIG. To the circuit 137 and the CRC generation circuit 134. After the input to the data service unit is completed in the CRC generation circuit 134 according to the output signal D-2 of the output signal control circuit 133. , Generation Polynomial G (x) = X ³² + X ²⁶ + X ²³ + X ²² + X ¹⁶ + X ¹² + X ¹¹ + X ¹⁰ + X ⁸ + X ⁷ + X ⁵ + X ⁴ + X ² + X + 1 A 4 octet CRC is generated and transmitted to be located at the end of the payload according to the output signal D-4 of the output signal control circuit 133.

The information length counter circuit 135 repeatedly calculates the modular-48 counter value according to the output signal D-1 of the output signal control circuit 133 and is provided from the media connection circuit 11 of FIG. If the buffer status signal BDEf is not notified, data length information of two octets, which is the length of a normal data service unit, is transmitted to the multiplexing circuit 137 in accordance with the output signal D-3.

When the redundant data generation circuit 136 is notified of the buffer status signal BDEf from the media connection circuit 11 of FIG. 1, the redundant data generation circuit 136 is configured for extra data for forming an information length of data in units of SAR-PDUs of 48 octets. The output of the redundant data generation circuit 136 is driven, and the redundant data that fills the excess length of the payload is transmitted to the multiplexing circuit 137 in accordance with the output signal D-1.

The multiplexing circuit 137 is a data service unit transmitted from the media connection circuit 11 of FIG. 1 in accordance with the output signal D-5, and surplus data transmitted from the surplus data generation circuit 136 transmitted as necessary; The data length information transmitted from the information length counter circuit 135 and the four octets of CRC provided by the CRC generation circuit 134 are multiplexed and transmitted to the output alignment circuit 138.

The output alignment circuit 138 transmits the data SAR-PDU to the media multiplexing circuit 14 of FIG. 1 according to the output signal D-6.

4 is a detailed block diagram of a header information buffer circuit, in which 41 is a header information setting circuit, 42 is an input signal selection circuit, and 43 is a header buffer.

As shown in the figure, the header information buffer circuit counts the header information input signal 1 provided from the system management circuit 15 of FIG. 1 to generate a header information setting signal. To generate the header buffer 43 and the ATM header which receive and store the header information output signal from the media cell multiplexing circuit 14 of FIG. 1 and supply the output header information to the media cell multiplexing circuit 14 of FIG. An input signal selection circuit 42 for selecting an input from the system management circuit 15 and the header buffer 43 of FIG.

Detailed description of the configuration is as follows.

The input signal selection circuit 42, the header information setting circuit 41, and the header buffer 43 are driven and switched by the management signal M3 of the system management circuit 15 of FIG. First, in the initial state, the input signal selection circuit 42 multiplexes the header information setting signal to receive the header information input signal 1 and 4 octets of input header information 1 transmitted from the system management circuit 15 of FIG. By controlling the output terminal of the circuit 42, the header information input signal 1 and the input header information are stored in the header buffer 43.

The header information setting circuit 41 composed of a counter controls the output terminal of the input signal multiplexing circuit 42 to indicate that the header input is completed according to the input header information input signal 1. Only the header information input signal 2 and the input header information 2 allow the output of the input signal multiplexing circuit 42. The header buffer 43 stores the input header information from the input signal multiplexing circuit 42 according to the header information input signal, and then header information according to the header information output signal provided from the media cell multiplexing circuit 14 of FIG. Is transmitted to the input signal multiplexing circuit 42 and the media cell multiplexing circuit 14 of FIG.

5 is a detailed block diagram of a media cell multiplexing circuit, in which 50 is a SAR media buffer, 51 is a SAR audio buffer, 52 is a SAR ISDN buffer, 53 is a SAR data buffer, 55 is a SAR buffer check circuit, and 56 is a media cell. A generating circuit, 57 denotes a media output selection circuit, 58 denotes a media cell multiplexing circuit, and 59 denotes an output alignment circuit.

As shown in the figure, the media cell multiplexing circuit includes a SAR media 50 for storing SAR-PDUs transmitted from the media generating circuit 12 of FIG. 1, and a buffer status signal SVBHf, SAR buffer checking circuit 55 for generating SABHf, SIBHf, SDBHf and generating an output buffer selection signal, and media cell generating circuit 56 for generating a cell generation signal upon receiving a drive signal from the SAR buffer checking circuit 55. ), A media output selection circuit 57 for controlling the cell generation signal of the media cell generation circuit 56 according to the output buffer selection signal from the SAR buffer checking circuit 55, the SAR media buffer 50 and the A media cell multiplexing circuit 58 for generating an ATM cell by combining the header input from the header information buffer 13 and the media SAR-PDU, and an output for sorting the media cells from the media cell multiplexing circuit 58; It consists of an alignment circuit 59.

Supplementary description of the configuration is as follows.

According to the management signal M4 and the status signal S4 of the system management circuit 15 of FIG. 1, the SAR image buffer 51, the SAR audio overloader 52, the SAR ISDN buffer 53, and the SAR data buffer 54 ), The SAR buffer check circuit 55, the media cell generation circuit 56, the media output selection circuit 57, the media cell multiplexing circuit 58, and the output alignment circuit 59 are driven and switched.

First, the SAR image buffer 51 stores a 48 octet image SAR-PDU transmitted from the media generation circuit 12 of FIG. 1, and then notifies the SAR buffer check circuit 55 of the buffer status signal SVBHf. The SAR audio buffer 52 stores the 48 octets of audio SAR-PDU transmitted from the media generating circuit 12 of FIG. 1, and then notifies the SAR buffer check circuit of the buffer status signal SABHf.

The SAR ISDN buffer 53 stores the 48 octets of ISDN SAR-PDUs transmitted from the media generation circuit 12 of FIG. 1, and then notifies the SAR buffer check circuit 55 of the buffer status signal (SIBHf) signal. The SAR data buffer 54 stores the data SAR-PDU transmitted from the media generating circuit 12 of FIG. 1, and then notifies the SAR buffer checking circuit 55 of the buffer status signal SDBHf. The SAR buffer checking circuit 55, which is composed of a logic circuit, a flip-flop, and a counter, receives the buffer status signals SVBHf, SABHf, SABHf, and SDBHf from the SAR buffers, and outputs an output buffer selection signal to the media output selection circuit 57. Transmits the media SAR-PDU to the media cell multiplexing circuit 58 by providing the output signals Vo-1, Ao-1, Io-1, Do-1 to the selected SAR buffer by transmitting to the media cell multiplexing circuit 58. do.

In the SAR buffer transmission circuit 55, the output buffer selection process is performed in the order of requiring a large bandwidth and real-time reconstruction on the receiving side. The priority is, first, the SAR image buffer 51, the SAR audio overlayer 52, and the SAR ISDN. The buffer 53 and finally the SAR data buffer 54 which does not require real time restoration are output in order. That is, the same operation is performed even when the buffer status signals SVBHf, SABHf, SIBHf, and SDBHf that are notified in the SAR media buffers 51, 52, 53, and 54 are received at the same time. As in the media unit generation unit 120 in FIG. 3, the media unit generation unit includes a counter circuit, a decoding circuit, and an output signal control circuit. Are sent to each SAR media buffer 51-54.

The media output selection circuit 57 is composed of a demultiplexer and a logic circuit and is transmitted to the respective SAR media buffers 51 to 54 through the selection circuit 57. The media output selection circuit 57 is composed of a demultiplexer and a logic circuit to output the cell generation signals (Vos, Aos, Ios, Dos) to the respective SAR media buffers and outputs according to the output buffer selection signal provided from the SAR buffer check circuit 55. The alignment circuit 59 and the header information buffer circuit 13 shown in FIG. As an example, a process of outputting an image cell includes receiving a buffer status signal SVBHf from a SAR image buffer 51 and receiving a Vo-1 signal through the media output signal selection circuit 57. The header information buffer circuit of FIG. 13), header information 1 is inputted to the media cell multiplexing circuit 58, and the SAR-PDU is outputted from the SAR image buffer 51 according to the Vo-2 signal, and multiplexed by the media cell multiplexing circuit 58 to 53 octets. Is transmitted to the output sorting circuit 59 in units of ATM cells, and transmission of audio and ISDN SAR-PDUs is also transmitted to the media cell multiplexing circuit 58 with the same header information 1. On the other hand, in case of data information, since the type of service is different at the variable bit rate recommended by CCITT, it should be transmitted on another channel. Through the Do-1 signal, the header information 2 from the header information buffer circuit 13 of FIG. 1 is input to the media cell multiplexing circuit 14 of FIG. 1, and from the Do-2 new circuit SAR data buffer 54. The data SAR-PDU is output, multiplexed by the media cell multiplexing circuit 58, and transmitted to the output sorting circuit 59 in units of ATM cells.

The output sorting circuit 59 aligns the ATM cells transmitted from the media cell multiplexing circuit 58 and transmits them to the physical layer according to Vo-3, Ao-4, Io-3, and Do-3 signals.

As described above, the present invention multiplexes a header having channel information, such as a fixed bit rate multimedia SAR-PDU, which requires a real time to be transmitted to an ATM network, and transmits the same to the ATM cell, and has a relatively low real-time data rate variable SAR-PDU. In addition, since the multiplexed headers having different channel information are transmitted to the ATM network, the ATM network can accommodate a fixed bit rate multimedia communication and data communication service.

Claims (9)

A media connection unit 11 for receiving a media connection from a fixed bit rate video codec, an audio codec, an ISDN terminal, and a data information source, and providing a media output signal to the media connection unit 11, thereby providing a media service unit and a buffer status signal. A media generating means (12) for receiving the SAR-PDU, providing the header information setting signal and the header information to the media generating means (12) and storing and providing the header information for the media (13); The header information buffering means 13 receives a header information setting signal and header information, receives a media SAR-PDU from the media generating means 12, and multiplexes the header and the media SAR-PDU to generate an ATM cell. A system management means (15) for managing connection with the media cell multiplexing means (14) and a network driving clock and an external control unit, and providing a management signal (Mi) to each circuit. Multimedia multiplexing device characterized in that it comprises a). The method according to claim 1, wherein the media connecting means (11); And a media buffering means (20) for storing media information input through the input means (29), and an input means (29) for input processing such as impedance matching of media information. . The method according to claim 2, wherein the input means (29) comprises; Image information input means 21 for inputting impedance matching by inputting NRZ image information, audio information input means 22 for inputting impedance matching by inputting NRZ audio information, ISDN information input means 23 for inputting impedance matching by inputting ISDN information, And data input means (24) for inputting data and impedance matching. The method of claim 2, wherein the media buffering means (20); Input the impedance-matched NRZ image information through the input means 29 and input the image output signal (V-5) from the media generating means 12 to output the image service unit and the buffer status signal BVHf The image information buffering means 25 and the input means 29 input the impedance matched NRZ audio information, and input the audio output signal A-5 from the media generating means 12 to the audio service unit and the buffer. Audio information buffering means 26 for outputting a status signal BAHf, input ISDN information impedance-matched through the input means 29, and input ISDN output signal I-5 from the media generating means 12; ISDN information input means 27 for outputting an ISDN service unit and a buffer status signal BIHf, and inputs impedance matched data through the input means 29, and outputs a data output signal from the media generating means 12. D-1) And a data buffering means (28) for outputting a data service unit and buffer status signals (BDHf, BDEf). The method according to claim 1, wherein the media generating means (12) comprises; Count means 122 for driving a counter by receiving buffer status signals BVHf, BAHf and BIHf from the media access means 2 for generating SAR-PDUs for fixed bit rate video and audio ISDN information. Decoding means 123 for decoding the counting output of 122, output signal control means 124 for generating a necessary output control signal in accordance with the decoding signal from the decoding means 123, and transmission from the media connection means 2; Timing information generating means 121 and timing information generating means 121 for generating timing information by receiving an input clock and a network clock of video, audio, and ISDN information, and output signals from the output signal control means 124. SAR header generation means 125 for receiving the timing information from the output signal and the output signal from the output signal control means 124 and generating a SAR header, and outputting from the output signal control means 124. A register 126 for receiving a signal and outputting a SAR header from the SAR header generating means 122, an output signal SAR header from the register 126 and 47 octets of media service from the media connecting means 11; Multiplexing means 20 for multiplexing the unit to generate a SAR-PDU, and an output sorting means for receiving an output signal from the output signal control means 124 and outputting and sorting the SAR-PDU from the multiplexing means 127. And a media generating circuit for video / audio / ISDN information having (128). 2. The apparatus according to claim 1, wherein the media generating means (12) is; In order to generate a SAR-PDU for variable bit rate data information, a buffer status signal (BDHf) is received from the media access means (11) and a header information setting signal from the header information buffering means (13) is driven to drive a counter. A counting means 131, decoding means 132 for decoding the counter output of the counting means 131, output signal control means for generating a necessary output control signal Ds in accordance with the decoding signal of the decoding means 132 ( 133, CRC generation means for receiving the output signals (D-2, D-4) from the output signal control means 133 and generating a 32-bit CRC for the information transmitted from the media connection means ( 134, the output signals D-1 and D-3 from the output signal control means 133 are received, and the output signal length BDE data from the media connection means 11 is counted to output data length information. Information length count In step 135, the output signal D-1 from the output signal control means 133 is inputted and the output signal BDEf from the media connection means 11 is received. Redundant data generating means 136 for filling in the remainder and outputting the surplus data, a data service unit receiving the output signal D-5 from the output signal control means 133, and receiving the output signal D-5 from the media connection means 11; Multiplexing means 137 for multiplexing excess data from said excess data generating means 136, data length information from said information length count means 135, and 4 octets of CRC from said CRC generating circuit 134; and An output sorting means 138 for receiving the output signal D-6 from the output signal control means 133 and receiving the multiplexed output signal from the multiplexing means 137 and transmitting it in units of SAR-PDUs; For data Multimedia multiplexing device, characterized in that the control comprises a generator. The method of claim 1, wherein the header information buffering means (13); Receiving header information output signal from the media cell multiplexing means 14 and the header information setting means 41 for generating the header information setting signal by counting the header information input signal 1 provided from the system management means 15; A header buffering means 43 for storing and supplying output header information to the media cell multiplexing means 14, and selecting an input from the system management means 15 and the header buffering means 43 to generate an ATM header. And an input signal selection means (42). 2. The apparatus of claim 1, further comprising: said media cell multiplexing means (14); SAR media buffering means 50 for storing the SAR-PDU transmitted from the media generating means 12, the buffer status signal (SVBHf, SABHf, SIBHf, SDBHf) is notified from the SAR media buffering means 50 output buffer From the SAR buffer checking means 55 for generating a selection signal, from the media cell generating means 56 and the SAR buffer checking means 55 for generating a cell generation signal in response to a drive signal from the SAR buffer checking means 55. Input from the media output selection means 57, the SDAR media buffering means 50, and the header information buffering means 13 for controlling the cell generation signal of the media cell generating means 56 in accordance with the output buffer selection signal of? And a media cell multiplexing means (40) for combining the header and the media SAR-PDU to generate an ATM cell, and an output sorting means (59) for output sorting the media cells from the media cell multiplexing means (58). to Multimedia multiplexing device. 9. The apparatus of claim 8, wherein the SAR media buffering means (50) comprises; SAR image which receives the image SAR-PDU from the media generating means 12 and receives the image output signal Vo2 from the media output selecting means 57 and outputs the SAR image buffer signal and the buffer status signal SVBHf. The SAR audio buffer signal and the buffer status signal SABHf are applied by the buffering means 51 and the audio SAR-PDU from the media generating means 12 and the audio output signal Ao2 from the media output selecting means 57. SAR audio over-performing means 52 for outputting the ISDN SAR-PDU from the media generating means 12 and ISDN output signal Io2 from the media output selecting means 57 for receiving the SAR ISDN buffer signal. And the SAR ISDN buffering means 53 for outputting the buffer status signal SIBHf, and the data SAR-PDU from the media generating means 12 and receiving the image output signal Vo2 from the media output selecting means 57. Licensed SAR Itaconic signal buffer and the buffer SAR data buffering multimedia multiplexing device, characterized in that includes means (54) for outputting a state signal (SDBHf).