KR950013095A - Receive bit error prevention circuit in multiple transmission systems - Google Patents

Receive bit error prevention circuit in multiple transmission systems Download PDF

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Publication number
KR950013095A
KR950013095A KR1019930022510A KR930022510A KR950013095A KR 950013095 A KR950013095 A KR 950013095A KR 1019930022510 A KR1019930022510 A KR 1019930022510A KR 930022510 A KR930022510 A KR 930022510A KR 950013095 A KR950013095 A KR 950013095A
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KR
South Korea
Prior art keywords
data
transmission systems
prevention circuit
error prevention
frequency
Prior art date
Application number
KR1019930022510A
Other languages
Korean (ko)
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KR950009423B1 (en
Inventor
최상열
Original Assignee
정장호
금성정보통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Priority to KR1019930022510A priority Critical patent/KR950009423B1/en
Publication of KR950013095A publication Critical patent/KR950013095A/en
Application granted granted Critical
Publication of KR950009423B1 publication Critical patent/KR950009423B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
    • H04L27/12—Modulator circuits; Transmitter circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop

Abstract

본 발명은 복수 송신 시스템에서의 수신 데이터의 에러 방지 회로에 관한 것으로, 특히 2개 이상의 송신 시스템에서 여러 주파수의 위상차에 의한 송신 데이터를 수신하는데 있어서 그 수신 데이터의 에러 발생율을 최소화하는데 적당하도록 한 것이다.The present invention relates to an error prevention circuit of received data in a plurality of transmission systems, and is particularly suitable for minimizing the error occurrence rate of the received data in receiving transmission data due to a phase difference of several frequencies in two or more transmission systems. .

종래의 기술은 복수 송신기(2개 이상의 송신기)에서 서로 다른 두 주파수인 제1반송파와 제2반송파의 진폭은 1비트 길이내에서 위상차가 거의 없는 부분에서는 서로 합해져서 크기가 커지게 되고 반면에 위상차가 많은(극성이 반대) 부분에서는 서로 상쇄되어 그 크기가 작아지게 되므로 원하는 데이터를 수신하지 못하고 엉뚱한 데이터를 수신하게 된다.In the prior art, the amplitudes of two different frequencies, a first carrier and a second carrier, in a plurality of transmitters (two or more transmitters) are added to each other and become larger in a portion where there is little phase difference within a length of 1 bit. In many (polarly opposite) parts, they cancel each other out and become smaller in size, so they do not receive the desired data and receive the wrong data.

따라서 본 발명은 송신 데이터와 합성되기 이전의 각각의 반송파에 송신신호를 일정 범위내에 주파수 위상편이 내에서 계속 변동시킬 수 있는 임의(Random) 저주파 편이를 걸어줌으로써 복수의 송신기로부터 수신되는 신호가 위상차로 인해 감쇄되는 영향을 최소화시켜 수신 신호의 불감 구간을 줄이도록 한 복수 송신 시스템에서의 수신 데이터의 에러 방지 회로를 구성한 것이다.Accordingly, in the present invention, a signal received from a plurality of transmitters is shifted out of phase by applying a random low frequency shift that can continuously change a transmission signal within a certain range within a frequency phase shift to each carrier before combining with transmission data. Therefore, an error prevention circuit of the received data in a plurality of transmission systems is configured to reduce the dead period of the received signal by minimizing the attenuation effect.

Description

복수 송신 시스템에서의 수신측 비트 에러 방지 회로Receive bit error prevention circuit in multiple transmission systems

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 의한 송신기 구성 회로 블럭도.3 is a block diagram of a transmitter configuration circuit according to the present invention.

제4도는 본 발명 복수 송신 시스템에서 서로 다른 두 주파수를 송신했을 경우 수신측에서의 1비트에 대한 신호 레벨의 변화 그래프.4 is a graph of change in signal level with respect to 1 bit at the receiver when two different frequencies are transmitted in the multiple transmission system of the present invention.

제5도는 본 발명을 실행하기 위한 두 송신 데이터간 듀티브 2/4인 경우의 참고도.5 is a reference diagram when the duty 2/4 between two transmission data for implementing the present invention.

제6도는 본 발명을 실행하기 위한 두 송신 데이터간 듀티브 3/4이상인 경우의 참고도.6 is a reference diagram when the duty is greater than or equal to 3/4 between two transmission data for implementing the present invention.

제7도은 본 발명에 의한 두 송신 데이터간 듀티비 1/5 이하인 경우의 참고도.7 is a reference diagram when the duty ratio 1/5 or less between two transmission data according to the present invention.

Claims (1)

반송파를 합성해내는 주파수 합성기부(10)와, 송신하고자 하는 2진 데이터(40)를 주파수 변조하는 주파수 변조 키잉부(30)와, 상기 주파수 합성기부의 반송파에 임의로 저주파 편이를 걸어주는 임의 저주파 발생기부(50)와, 상기 저주파 편이된 반송파에 2진 데이터를 합성하고 전압 제어 발진하여 채널 주파수를 형성하는 합성 및 전압 제어 발진부(20)로 구성하는 것을 특징으로 하는 복수 송신 시스템에서의 수신측 비트 에러 방지 회로.A frequency synthesizer unit 10 for synthesizing a carrier wave, a frequency modulation keying unit 30 for frequency modulating the binary data 40 to be transmitted, and an arbitrary low frequency station that arbitrarily applies a low frequency shift to a carrier wave of the frequency synthesizer unit Receiving side in a multiple transmission system comprising a generator section 50 and a synthesizing and voltage controlled oscillator 20 for synthesizing binary data to the low frequency shifted carrier and performing voltage controlled oscillation to form a channel frequency. Bit error prevention circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930022510A 1993-10-27 1993-10-27 Bit error preventing circuit in multi transmission systems KR950009423B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930022510A KR950009423B1 (en) 1993-10-27 1993-10-27 Bit error preventing circuit in multi transmission systems

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930022510A KR950009423B1 (en) 1993-10-27 1993-10-27 Bit error preventing circuit in multi transmission systems

Publications (2)

Publication Number Publication Date
KR950013095A true KR950013095A (en) 1995-05-17
KR950009423B1 KR950009423B1 (en) 1995-08-22

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930022510A KR950009423B1 (en) 1993-10-27 1993-10-27 Bit error preventing circuit in multi transmission systems

Country Status (1)

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KR (1) KR950009423B1 (en)

Also Published As

Publication number Publication date
KR950009423B1 (en) 1995-08-22

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