KR950012739B1 - Esd protection device - Google Patents

Abstract

a second conduction type of well which is formed on a first conduction type of substrate; a first conduction type of a high density of impurity area and the second conduction type of a first high density impurity area which are formed in the interior of the second conduction type of well; the second conduction type of a second high density impurity area which are formed in the boundary surface between the first conduction type of substrate and the second conduction type of well; the second conduction type of a third high density impurity area which are formed in the first conduction type of substrate; the first conduction type of substrate formed between the second conduction type of the second high density impurity area and the second conduction type of the third high density impurity area; and an insulating film formed on the second conduction type of well between the second conduction type of the second high density impurity area and the first conduction type of the high density impurity area.

Description

ESD protection device

1 is a cross-sectional view of a protection circuit using the SCR of the conventional first embodiment.

2 is a cross-sectional view of a structure of a protection circuit using the SCR of the related art.

3 is a cross-sectional view of a protection circuit using the field transistor of the conventional third embodiment.

4 is a plan view of the ESD protection device of the present invention.

5 is a cross-sectional view of the ESD protection device of the present invention.

6 is a cross-sectional view of an ESD protection device of the present invention.

* Explanation of symbols for main parts of the drawings

11 substrate 12 well

13 field oxide film 14 gate insulating film

15: gate electrode 16a, 16b, 16c: low concentration n-type ion implantation

17 side wall 18 high concentration n-type ion implantation region

19a, 19b, 19c: high concentration n-type impurity region

20: high concentration p-type impurity region 21: insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic discharge (ESD) protection circuit, and more particularly, to protection of an internal circuit of a chip suitable for improving ESD resistance using a silicon controlled rectifier (SCR).

In general, the ESD protection circuit is a method using an SCR, a field transistor (diode), a bipolar transistor (bipolar transistor) and the like method to protect the internal circuit from static electricity of 200 ~ 2000V.

A conventional ESD protection circuit will be described with reference to the accompanying drawings.

1 is a cross-sectional view of a structure of a protection circuit using an SCR according to a conventional embodiment, in which an n-type well 2 is formed by n-type ion implantation on a predetermined portion of a p-type substrate 1, and n An ion implantation process forms a first high concentration n-type impurity region 3 and a first high concentration p-type impurity region 4 in an ion well, and the second high concentration n-type impurity region 5 and a second high concentration n-type well 2 are formed. Two concentration p-type impurity regions 6 are formed.

The pad PAD is connected to the first high concentration n-type impurity region 3 and the first high concentration p-type impurity region 4 in the n-type well 2, and the second high concentration n-type impurity region 5 and The second high concentration p-type impurity region 6 is grounded in common.

In the conventional protection circuit configured as described above, a PNP transistor including a p-type substrate 1, an n-type well 2, and a first high concentration p-type impurity region is formed as shown by a dotted line, and the n-type well 2 and p-type substrate 1 ) And a second high concentration n-type impurity region (5), and an n-type well (2), a first high-concentration n-type impurity region (3), a P-type substrate (1) and a second high-concentration p-type impurity A resistance structure is comprised between the areas 6.

In this way, the SCR device is formed, and the SCR is triggered by the breakdown of the PN junction to protect the internal circuit by operating the junction of the n-type well and the p-type substrate in turn.

2 is a schematic cross-sectional view of an ESD protection circuit according to a conventional second embodiment, wherein the structure is the same as that of the first diagram, but the third high concentration n-type impurity region is formed in the junction of the n-type well 2 and the p-type substrate 1 on the surface in order to lower the breakdown voltage. (7) is formed and a transistor 8 having a thin gate oxide film 9 is formed between the third high concentration n-type impurity region 7 and the second high concentration n-type impurity region 5.

3 is a cross-sectional view of a structure of a protection circuit using a field transistor according to a third embodiment of the present invention, in which a plastic field transistor is formed between a well and a well and a junction and a well in order to lower the breakdown voltage or the same principle as those of FIGS. It lowers the breakdown voltage and specifically isolates the SCRs that are driven by the positive and negative ESD pulses.

However, the ESD protection circuit of the conventional embodiments has the following problems.

First, the ESD protection circuit according to the first embodiment of the first embodiment, such as the first diagram, has to be about 100V when 2000V is applied to discharge the ESD energy, and the trigger voltage of the SCR is 50V or more, so it is 64M DRAM or more. Since the thickness of the gate oxide film in the semiconductor device is 100 kΩ or less, if the gate oxide film is taken over 15V, the gate oxide film is taken over 50V or more, thereby preventing the internal circuit from being protected.

Second, in the ESD protection circuit of the second embodiment, such as the second diagram, a high concentration n on the surface of the ESD protection circuit of FIG. 1 to improve the high breakdown voltage between the n-type well 2 and the p-type substrate 1 of FIG. The type impurity region 7 is formed and the transistor is formed to be lowered to about 10 V. However, since the transistor 8 and the third high concentration n-type high concentration impurity region 7 are adjacent to each other, the third high concentration n-type impurity region 7 The thin gate oxide film 9 is easily broken by the hot carrier.

Third, in the ESD protection circuit of the third embodiment, such as the third diagram, the plastic field transistor can be used to lower the trigger voltage of the SCR and increase the operating speed of the SCR. However, the gate of the plastic field transistor can be operated between 27.6 and 44.7V. When the insulating film is 100 kPa or less, it is difficult to use.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object thereof is to speed up an SCR operation and to improve ESD resistance.

In order to achieve the above object, the ESD protection device of the present invention includes a second conductivity type well formed in a first conductivity type substrate, a first concentration type impurity region and a second conductivity type formed inside the second conductivity type well. A first high concentration impurity region of a second conductivity type, a second high concentration impurity region of a second conductivity type formed at an interface between the first conductivity type substrate and the second conductivity type well, and a second conductivity type formed on the first conductivity type substrate The first conductive substrate between the third high concentration impurity region, the second high concentration impurity region of the second conductivity type, the third high concentration impurity region of the second conductivity type, and the second high concentration of this second conductivity type And an insulating film formed in the second conductivity type well between the impurity region and the high concentration impurity region of the first conductivity type.

This invention is described in detail with reference to the accompanying drawings as follows.

4 is described in detail with reference to the accompanying drawings of the present invention.

4 is a layout diagram of the ESD protection circuit of the present invention, FIG. 5 is a cross-sectional view taken along line AA ′ of FIG. 4, and FIG. 6 is a process cross-sectional view taken along line AA ′ and BB ′ of FIG. 4. The protection circuit is divided into a first clamp circuit portion (A) for releasing the applied energy to the substrate when a high voltage is applied to the pad, and a second clamp circuit for clamping the voltage passing through the first clamp circuit and the diffusion resistor, and the first clamp circuit portion. Between (A) and the second clamp circuit portion (c), a diffusion resistance region (B) for enhancing the voltage passing through the first clamp circuit portion (A) is formed.

FIG. 6 is a cross-sectional structure of the first clamp circuit A-A 'of FIG. 4 and a cross-sectional structure of the second clamp circuit BB', and shows the ESD protection circuit process of the present invention. Likewise, the first clamp circuit region forms the n-type well 12 by n-type ion implantation in the p-type substrate 11 and defines the field region and the active region as shown in FIG. 13), a gate oxide film 14 is grown on the second clamp circuit portion, and a gate 15 is formed thereon, and then between the n-type well 12, the n-type well 12 and the substrate 11, and the engine. Low concentration n-type ion implantation 16a, 16b, and 16c are respectively performed in the process.

As shown in FIG. 6 (c), the sidewalls 17 are formed in the gate 15 of the second clamp circuit, and the first, second and third high concentration n-type impurity regions 19a and 19b are formed by the high concentration n-type ion implantation in the same region. , 19c).

At this time, the diffusion resistance of FIG. 4 is also formed.

As shown in FIG. 6 (d), a high concentration of p-type impurity region 20 is formed by implanting p-type ions into the n-type well 12, and then the insulating film 21 is deposited on the entire surface as shown in FIG. 6 (e). In addition, after forming contact holes in the third high concentration impurity regions 19a and 19c and the high concentration p-type impurity region 20 and the like, metal is deposited to form metal electrodes 22 at the respective portions.

In the ESD protection circuit of the present invention as described above, the SCR is triggered by the second high concentration n-type impurity region 19b to which the n-type well is connected. Also, since the breakdown voltage is 10V or less, the triggering is faster than the conventional breakdown voltage of 30 to 40V and the SCR operation is faster, thereby effectively protecting the internal circuit.

Claims (2)

A second conductivity type well formed in the first conductivity type substrate, a high concentration impurity region of the first conductivity type formed in the second conductivity type well, a first concentration impurity region of the second conductivity type, and the first conductivity type substrate And a second high concentration impurity region of a second conductivity type formed at an interface between the second conductivity type well, a third high concentration impurity region of a second conductivity type formed on the first conductivity type substrate, and a second conductivity type Between the second high concentration impurity region and the second high concentration impurity region of the second conductivity type, the second high concentration impurity region of the second conductivity type, and the high concentration impurity region of the first conductivity type ESD protection device comprising an insulating film formed in the second conductivity type well of the. Forming a second conductivity type well in a first conductivity type substrate, forming a first field insulation film and a second field insulation film in the first conductivity type substrate and the second conductivity type well, and a second conductivity type Ion implantation of the second conductive well to the second conductive well to form a second high conductivity impurity region; and the first conductive substrate to a second high concentration impurity region of the second conductivity type as the first field insulating film. Forming an isolated second conductive impurity region of the second conductivity type, and implanting the first conductive ion into the second conductive well to form the second conductive impurity region in the second conductive well; And forming a high concentration impurity region of a first conductivity type separated by two field insulating films.