KR950011307B1 - Focus compensation circuit of monitor - Google Patents
Focus compensation circuit of monitor Download PDFInfo
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- KR950011307B1 KR950011307B1 KR1019920014857A KR920014857A KR950011307B1 KR 950011307 B1 KR950011307 B1 KR 950011307B1 KR 1019920014857 A KR1019920014857 A KR 1019920014857A KR 920014857 A KR920014857 A KR 920014857A KR 950011307 B1 KR950011307 B1 KR 950011307B1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
- H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
- H04N3/16—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
- H04N3/26—Modifications of scanning arrangements to improve focusing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K4/00—Generating pulses having essentially a finite slope or stepped portions
- H03K4/04—Generating pulses having essentially a finite slope or stepped portions having parabolic shape
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
- H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
- H04N3/16—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
- H04N3/18—Generation of supply voltages, in combination with electron beam deflecting
Abstract
Description
제 1 도는 종래 모니터의 포커스 조정회로도.1 is a focus adjustment circuit diagram of a conventional monitor.
제 2 도는 제 1 도에 따른 파형도.2 is a waveform diagram according to FIG.
제 3 도는 본 발명 모니터의 포커스 자동보정회로도.3 is a focus automatic circuit correction diagram of the monitor of the present invention.
제 4 도는 제 3 도에 따른 각부의 파형도.4 is a waveform diagram of each part according to FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 수평출력부 2 : 정전압출력부1: horizontal output unit 2: constant voltage output unit
3,13 : 발진부 4,17 : 위상반전부3,13: oscillation part 4,17: phase inversion part
5,18 : 스태틱포커스회로 10 : 수평동기입력부5,18: Static focus circuit 10: Horizontal synchronous input unit
11 : 동기극성판별부 12 : F/V변환부11: Synchronous polarity discrimination part 12: F / V conversion part
13 : 발진부 14 : 신호스위칭부13 oscillation unit 14: signal switching unit
15 : 적분회로 16 : 클램핑 회로15: integrating circuit 16: clamping circuit
18 : 스태틱포커스회로 QP1: 연산증폭기18: static focus circuit QP 1 : operational amplifier
Q1,Q2,Q11-Q13: 트랜지스터 L1: 코일Q 1 , Q 2 , Q 11 -Q 13 : Transistor L 1 : Coil
L2: 수평편향코일 D1,D11,D12: 다이오드L 2 : horizontal deflection coil D 1 , D 11 , D 12 : diode
ZD11,ZD12: 제너다이오드 VR1, VR11: 가변저항ZD 11 , ZD 12 : Zener Diode VR 1 , VR 11 : Variable Resistor
C1-C+,C11-C16: 콘덴서 R1-R13: 저항C 1 -C + , C 11 -C 16 : Capacitor R 1 -R 13 : Resistance
본 발명은 모니터의 수평편향 출력회로에 관한 것으로, 특히 티브이나 모니터에서 수평주사주파수에 관계없이 일정한 파라볼라전압을 출력하여 자동으로 포커스를 보정하는 모니터의 포커스 자동보정회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal deflection output circuit of a monitor, and more particularly, to a focus auto correction circuit of a monitor that automatically corrects focus by outputting a constant parabola voltage regardless of a horizontal scan frequency in a TV or monitor.
제 1 도는 종래 모니터의 포커스 조정회로도로서 이에 도시한 바와같이, 수평출력부(1)의 수평동기신호(Hsyn)에 따라 턴온, 턴오프하여 수평출력펄스(Vq)를 출력하는 트랜지스터(Q1), 다이오드(D1)와 콘덴서(C1)로 구성되어 상기 트랜지스터(Q1)의 출력(Vq)을 정류하여 직류전압(Vd)을 출력하는 정전압출력부(2)와, 코일(L1), 수평편향코일(L2) 및 콘덴서(C2)로 구성되어 상기 트랜지스터(Q1)의 출력(Vq)에 공진되어 수평출력파라볼라신호(Vp)를 출력하는 발진부(3)와, 트랜지스터(Q2), 저항(R3-R9) 및 콘덴서(C3), (C+)로 구성되어 상기 정전압출력부(2)의 출력(Vd)을 입력받고 발진부(3)의 출력(Vp)이 입력됨에 따라 위상을 반전시켜 포커스전극(G+)과 스태틱포커스회로(5)에 출력하는 위상반전부(4)로 구성된 것으로, 상기 스태틱포커스회로(5)는 위상반전부(4)의 출력(Vip)을 입력받아 화면의 화질을 조정하도록 저항(R1),(R2) 및 가변저항(VR1)으로 구성된다.FIG. 1 is a focus adjustment circuit diagram of a conventional monitor. As shown therein, a transistor Q 1 which turns on and off in accordance with a horizontal synchronization signal Hsyn of the horizontal output unit 1 and outputs a horizontal output pulse V q . ), A diode (D 1 ) and a capacitor (C 1 ) and a constant voltage output unit (2) for rectifying the output (V q ) of the transistor (Q 1 ) to output a DC voltage (V d ), and the coil ( L 1), a horizontal deflection coil (L 2) and a condenser (composed of C 2) oscillation unit (3) for outputting a horizontal output parabola signal (V p) is resonant to the output (V q) of the transistor (Q 1) And a transistor (Q 2 ), a resistor (R 3 -R 9 ), a capacitor (C 3 ), and (C + ) to receive the output (V d ) of the constant voltage output unit (2) and receive the oscillation unit (3). Is composed of a phase inversion part 4 which inverts the phase as the output V p is inputted and outputs it to the focus electrode G + and the static focus circuit 5, wherein the static focus circuit 5 is phased. Resistor (R 1 ), (R 2 ) and variable resistor (VR 1 ) is configured to receive the output (Vip) of the inverting unit 4 to adjust the image quality of the screen.
이와같이 구성된 종래 회로의 동작과정을 제 2 도의 파형도를 참조하여 설명하면 다음과 같다.An operation process of the conventional circuit configured as described above will be described with reference to the waveform diagram of FIG. 2.
먼저, 수평출력회로(1)의 수평동기신호(Hsyn)가 베이스에 입력됨에 따라 트랜지스터(Q1)가 턴온, 턴오프되어 수평출력펄스(Vq)가 정전압출력부(2)와 발진부(3)에 출력되고 상기 정전압출력부(2)에서 상기 수평출력펄스(Vq)가 다이오드(D1)를 통해 정류되어 콘덴서(C1)에서 평활됨으로써 직류전압(Vd)으로 위상반전부(4)의 트랜지스터(Q2)의 베이스와 콜렉터에 출력된다.First, as the horizontal synchronizing signal Hsyn of the horizontal output circuit 1 is input to the base, the transistor Q 1 is turned on and off so that the horizontal output pulse V q is the constant voltage output unit 2 and the oscillation unit 3. ) And the horizontal output pulse (V q ) in the constant voltage output unit (2) is rectified through the diode (D 1 ) and smoothed in the capacitor (C 1 ) to the phase inversion unit (4) with a DC voltage (V d ) Is output to the base and collector of the transistor Q 2 .
이때, 발진부(3)는 트랜지스터(Q1)의 수평출력펄스(Vq)가 입력됨에 따라 코일(L1)에서 전류가 조정되어 편향코일(L2)과 콘덴서(C2)에 의해 공진됨에 따라 제 2 도 (가)에 도시된 바와같은 수평출력 파라볼라신호(Vp)가 발생되고 상기 수평출력파라볼라신호(Vp)는 위상반전부(4)의 저항(R9)과 콘덴서(C3)를 통해 직류 성분을 제거되어 트랜지스터(Q2)의 베이스에 출력된다.At this time, the oscillation unit 3 is adjusted by the current in the coil (L 1 ) as the horizontal output pulse (V q ) of the transistor (Q 1 ) is resonated by the deflection coil (L 2 ) and the capacitor (C 2 ) Accordingly, a horizontal output parabolic signal V p is generated as shown in FIG. 2A, and the horizontal output parabolic signal V p is generated by the resistor R 9 and the condenser C 3 of the phase inversion unit 4. The direct current component is removed and output to the base of the transistor Q 2 .
그리고, 베이스에 정현파인 수평출력파라볼라신호(Vp)가 입력된 트랜지스터(Q2)가 턴온, 턴오프되어 콜렉터로 위상이 반전됨과 아울러 증폭된 제 2 도 (나)에 도시된 바와같은 파라볼라파형의 전압(Vip)이 발생된다.In addition, the transistor Q 2 having the sinusoidal horizontal output parabolic signal V p is turned on and turned off to invert the phase to the collector, and the parabolic waveform shown in FIG. 2B is amplified. The voltage Vip is generated.
따라서 위상반전부(4)의 출력(Vip)은 포커스전극(G+) 에 출력됨과 아울러 스태틱(Static)포커스회로(5)에 출력되고 가변저항(VR1)이 조정된 상기 스태틱포커스회로(5)를 통해 포커스가 보정되어 화면 전체에 고른 화질을 나타낸다.Accordingly, the output Vip of the phase inversion unit 4 is output to the focus electrode G + and to the static focus circuit 5 and the static focus circuit 5 in which the variable resistor VR 1 is adjusted. ), The focus is corrected to show an even image quality across the screen.
그러나, 이와같은 종래 회로의 수평주파수가 31KHz의 단일 주사주파수일때는 포서크 보정에 별 문제가 없으나 고해상도 고화질을 요구하는 모니터에서는 31KHz-80KHz의 광대역 수평주사주파수에 따른 수평동기신호가 입력되기 때문에 포커스를 보정하기 위해서는 공진주파수를 변경하여야 하나 공진주파수가 편향코일과 공진콘덴서에 의해 결정됨으로 공진주파수의 변경이 용이하지 않은 문제점이 있다.However, when the horizontal frequency of such a conventional circuit is a single scan frequency of 31 KHz, there is no problem in forcing correction, but a monitor requiring high resolution and high quality inputs a horizontal synchronization signal according to a wide bandwidth horizontal scanning frequency of 31 KHz to 80 KHz. In order to compensate for this problem, the resonance frequency must be changed, but the resonance frequency is determined by the deflection coil and the resonance capacitor.
또한, 수평주사주파수가 높으면 편향코일의 인덕턴스가 크게되어 포커스를 보정하기 위해 대진폭의 파라볼라전압을 출력해야 함으로 출력트랜지스터의 콜렉터 손실이 크게 되는 문제점이 있다.In addition, if the horizontal scan frequency is high, the inductance of the deflection coil is large, and a large amplitude parabola voltage must be output to correct the focus, thereby causing a large collector loss of the output transistor.
본 발명은 이러한 문제점을 감안하여 수평주파수에 관계없이 항상 일정한 수평출력 파라볼라전압을 발생시켜 자동으로 포커스를 보정하는 모니터의 포커스 자동보정회로를 창안한 것으로, 이를 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.SUMMARY OF THE INVENTION In view of these problems, the present invention has been made a focus auto-correction circuit for a monitor that automatically corrects focus by always generating a constant horizontal output parabolic voltage regardless of the horizontal frequency. Same as
제 3 도는 본 발명 모니터의 포커스 자동보정회로도로서 이에 도시한 바와같이, 트랜지스터(Q11), 저항(R1),(R2) 및 콘덴서(C11)로 구성하여 수평동기신호(Hsyn)가 입력하에 따라 반전시키는 수평동기입력부(10)와, 수평동기입력부(10)의 출력(Hi)을 입력받아 극성을 판별하여 정극성동기신호(V1)를 출력하는 동기극성판별부(11)와, 이 동기극성판별부(11)의 출력(V1)을 직류전압(Vd)으로 변환하는 주파수(Frequency)/전압(Voltage)변화부(12)와, 상기 동기극성판별부(11)의 출력(V1)이 입력함에 따라 구형파(V2)를 발생시키는 발진부(13)와, 트랜지스터(Q12) 및 저항(R+)으로 구성하여 상기 발진부(13)의 출력(V2)이 입력함에 따라 반전시키는 신호스위칭부(14)와, 연산증폭기(OP1), 콘덴서(C13),(C1 +) 및 저항(R6)으로 구성하여 상기 신호스위칭부(14)의 출력(V3)을 적분하여 톱니파전압(V+)을 출력하는 적분회로(15)와, 제너다이오드(ZD11),(ZD12) , 다이오드(D11),(D12) 및 저항(R7-R9)으로 구성하여 상기 적분회로(15)의 출력(V9)을 클램핑하여 파라볼라신호(V6)를 입력받아 파형보정한 반전파라보라신호(V7)를 포커스전극(G+)과 스태틱포커스회로(18)에 출력하는 위상반전부(17)로 구성한 것으로, 이와같은 본 발명의 작용 및 효과를 제 4 도 각부의 파형도를 참조하여 상세히 설명하만 다음과 같다.3 is a focus automatic correction circuit diagram of a monitor according to the present invention. As shown in FIG. 3, the horizontal synchronization signal Hsyn is composed of a transistor Q 11 , a resistor R 1 , a R 2 , and a capacitor C 11 . A horizontal synchronous input unit 10 for inverting according to the input, a synchronous polarity discriminating unit 11 for outputting the positive polarity synchronous signal V 1 by discriminating the polarity by receiving the output Hi of the horizontal synchronous input unit 10, the output of the sync polarity determination unit 11, the output (V 1), a DC voltage frequency to be converted to (V d) (frequency) / voltage (voltage) change unit 12 with the sync polarity determination unit 11, As the V 1 inputs, the oscillator 13 generates a square wave V 2 , and the transistor Q 12 and the resistor R + are configured to be input by the output V 2 of the oscillator 13. the output of the signal switching unit 14 for inverting a result, the operational amplifier (OP 1), the capacitor (C 13), (C 1 +) and configured as a resistance (R 6), the signal switching unit 14 (V 3 Enemy Integrator circuit 15 for dividing and outputting sawtooth wave voltage (V + ), zener diodes (ZD 11 ), (ZD 12 ), diodes (D 11 ), (D 12 ) and resistors (R 7 -R 9 ) In this configuration, the output V 9 of the integrating circuit 15 is clamped to receive the parabola signal V 6 , and the inverted parabolic signal V 7 obtained by waveform correction is used for the focus electrode G + and the static focus circuit 18. The phase inverting unit 17 outputs to the above) is described in detail with reference to the waveform diagram of each part of FIG. 4 as follows.
먼저, 수평동기입력부(10)에 수평동기신호(Hsyn)가 입력하면 병렬접속된 저항(R1) 및 콘덴서(C1)를 통해 스피드업시켜 트랜지스터(Q11)를 턴온, 턴오프시킴으로써 상기 트랜지스터(Q11)의 콜렉터에서 반전된 신호(Hi)가 동기극성판별부(11)에 출력한다.First, when the horizontal synchronous signal Hsyn is input to the horizontal synchronous input unit 10, the transistor Q 11 is turned on and turned off by speeding up through a parallel connected resistor R 1 and a capacitor C 1 . The signal Hi inverted by the collector of Q 11 is output to the synchronous polarity discrimination section 11.
이때, 동기극성판별부(11)는 수평동기입력부(10)의 출력(10)을 입력받아 동기극성에 관계없이 제 4(a) 도에 도시한 바와같은 정극성동기신호(V1)를 F/V변환부(12)와 발진부(13)에 출력한다.At this time, the synchronous polarity determining unit 11 receives the output 10 of the horizontal synchronous input unit 10 and receives the positive synchronous signal V 1 as shown in FIG. 4 (a) regardless of the synchronous polarity. Output to the V converter 12 and the oscillator 13.
따라서, F/V변환부(12)는 동기극성판별부(11)의 동기주파수(V1)가 입력함에 따라 제 4(b) 도에 도시한 바와같은 직류전압(Vd) 성분으로 변환하는데 상기 동기주파수(V1)가 높을수록 큰 직류성분(Vd)을 신호스위칭부(14)의 트랜지스터(Q12)의 콜렉터와 위상반전부(17)의 트랜지스터(Q13)의 콜렉터 및 베이스에 출력하여 바이어스전압으로 설정한다.Accordingly, the F / V converter 12 converts the DC voltage V d as shown in FIG. 4 (b) as the synchronous frequency V 1 of the synchronous polarity discrimination unit 11 is input. As the synchronous frequency V 1 increases , a large DC component V d is applied to the collector of the transistor Q 12 of the signal switching unit 14 and the collector and base of the transistor Q 13 of the phase inversion unit 17. Output to set bias voltage.
또한, 발진부(13)는 동기극성판별부(11)의 정극성동기신호(V1)가 구형파발진기(13-1)의 단자(P1)에 입력함에 상기 구형파발진기(13-1)가 동작하여 가변저항(VR11)과 콘덴서(C12)의 시정수에 따른 일정한 진폭의 구형파(V2)를 단자(D+)로 출력한다.In addition, the oscillator 13 operates the square wave oscillator 13-1 by inputting the positive synchronous signal V 1 of the synchronous polarity discrimination unit 11 to the terminal P 1 of the square wave oscillator 13-1. A square wave V 2 having a constant amplitude according to the time constant of the variable resistor VR 11 and the capacitor C 12 is output to the terminal D + .
이때, 제 4(c) 도에 도시한 바와같은 발진부(13)의 구형파(V2)를 입력받아 신호스위칭부(14)의 트랜지스터(Q12)가 턴온, 턴오프하여 상기 트랜지스터(Q12)의 콜렉터에서 제 4(d) 도에 도시한 바와같이 위상이 반전된 구형파(V2)가 적분회로(15)에 출력한다.In this case, the 4 (c) by the transistor (Q 12) for receiving the square wave (V 2) of the oscillation unit 13, signal switching unit 14 is turned on, turning off the transistor (Q 12) as shown in Fig. the output at the collector of claim 4 (d) also by a square wave (V 2) the integrating circuit 15, the phase is inverted as shown in Fig.
이에따라, 신호스위칭부(14)의 출력(V3)을 입력받은 적분회로(15)는 콘덴서(C13)에서 직류 성분을 제거한 교류성분만을 저항(R6)을 통해 연산증폭기(OP1)의 반전단자에 입력시켜 적분함으로써 제 4(e) 도에 도시한 바와같은 톱니파전압(V+)을 클램핑회로(16)에 출력한다.Accordingly, the integrating circuit 15 receiving the output V 3 of the signal switching unit 14 has only the AC component having the DC component removed from the capacitor C 13 of the operational amplifier OP 1 through the resistor R 6 . By inputting to the inverting terminal and integrating, the sawtooth wave voltage V + as shown in FIG. 4 (e) is output to the clamping circuit 16.
이때, 적분회로(15)의 톱니파 전압을 입력받은 클램핑회로(16)는 다이오드(D11) 및 제너다이오드(ZD11)를 통해 클램핑한 제 4(f) 도에 도시한 바와같은 신호(V5)를 발생시키고 다이오드(D12) 및 제너다이오드(ZD12)를 통해 상기 신호(V5)를 클램핑하여 제 4(g) 도에 도시한 바와같은 수평출력파라볼라신호(V6)를 위상반전부(17)에 출력한다.At this time, the clamping circuit 16 receiving the sawtooth wave voltage of the integrating circuit 15 has the signal V 5 as shown in FIG. 4 (f) clamped through the diode D 11 and the zener diode ZD 11 . ) And clamps the signal V 5 through the diode D 12 and the zener diode ZD 12 to phase shift the horizontal output parabolic signal V 6 as shown in FIG. 4 (g). Output to (17).
따라서, 위상반전부(17)는 클램핑회로(16)의 출력(V0)을 콘덴서(C15)를 통해 직류성분을 제거하고 트랜지스터(Q13)의 베이스에 입력시켜 상기 트랜지스터(Q13)를 턴온, 턴오프시킴으로써 그 콜렉터로 제 4(h) 도에 도시한 바와같은 위상반전된 파라볼라전압(V7)을 발생시킨다.Therefore, the output (V 0), the transistor (Q 13) to the input to the base of the removal of the DC component through a capacitor (C 15) and a transistor (Q 13) of the phase inverting portion 17 has a clamping circuit 16 By turning on and off, the collector generates a phase inverted parabola voltage V 7 as shown in FIG. 4 (h).
이때, 트랜지스터(Q13)의 콜렉터에 F/V변환부(12)의 출력직류전압(Vd)의 바이어스전압으로 입력하기 때문에 수평동기입력부(10)에 입력되는 수평동기주파수(Hsyn)가 높으면 높을수록 위상반전부(17)의 파라볼라전압(V7)은 크게 발생하고 낮으면 낮을수록 파라볼라전압(V7)은 적게 발생한다.At this time, since the bias voltage of the output DC voltage V d of the F / V converter 12 is input to the collector of the transistor Q 13 , the horizontal synchronous frequency Hsyn input to the horizontal synchronous input unit 10 is high. The higher the parabolic voltage V 7 of the phase inversion unit 17 is generated, the lower the lower the parabola voltage V 7 is generated.
이에따라, 수평동기주파수에 관계없이 항상 일정한 진폭의 파라볼라전압(V7)을 콘덴서(C6)를 통해 스태틱포커스회로(18)와 포커스전극(G+)에 출력하여 모니터 전체의 포커스를 보정한다.Accordingly, the parabolic voltage V 7 having a constant amplitude is always output to the static focus circuit 18 and the focus electrode G + through the capacitor C 6 to correct the focus of the entire monitor regardless of the horizontal synchronization frequency.
상기에서 상세히 설명한 바와같이 본 발명 모니터의 포커스 자동보정회로는 입력되는 수평동기주파수를 직류전압으로 변환하여 바이어스전압으로 하고 수평동기주파수에 관계없이 항상 일정한 진폭의 파라볼라전압을 발생시켜 포커스를 자동으로 보정함으로써 수평출력트랜지스터의 콜렉터 손실을 줄여 수평출력회로의 손실을 감소시키는 효과가 있다.As described in detail above, the focus auto-correction circuit of the present invention converts the horizontal synchronous frequency input into a DC voltage to be a bias voltage and automatically corrects the focus by always generating a parabola voltage having a constant amplitude regardless of the horizontal synchronous frequency. As a result, the loss of the horizontal output transistor can be reduced by reducing the collector loss of the horizontal output transistor.
Claims (5)
Priority Applications (1)
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KR1019920014857A KR950011307B1 (en) | 1992-08-18 | 1992-08-18 | Focus compensation circuit of monitor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1019920014857A KR950011307B1 (en) | 1992-08-18 | 1992-08-18 | Focus compensation circuit of monitor |
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KR940005168A KR940005168A (en) | 1994-03-16 |
KR950011307B1 true KR950011307B1 (en) | 1995-09-30 |
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KR1019920014857A KR950011307B1 (en) | 1992-08-18 | 1992-08-18 | Focus compensation circuit of monitor |
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