KR950010568B1 - Memory array structure of dram - Google Patents

Abstract

The memory array structure of DRAM comprises a first memory array region, a second memory array region, a plurality of bit line pairs connected to the memory cells of the first and second memory array regions, a plurality of word lines, a plurality of sense amplifiers for sensing/amplifying the voltage difference between two bit lines, a plurality of P latches connected between bit line pairs of the first memory array region, a plurality of first equalizers for precharging the bit line pair to 1/2VDD voltage according to a first equalizer signal, a plurality of N latches connected between bit line pairs of the second memory array region, a plurality of second equalizers for precharging the bit line pair to 1/2VDD voltage according to a second equalizer signal, a plurality of barrier transistors for equalizing the bit line voltage of the first and second memory regions according to the pull-up of the first and second control signals or the third and fourth control signals.

Description

DRAM memory array structure

1 is a conventional folded bit line structure and noise equivalent circuit diagram.

2 is a conventional twisted bit line structure and noise equivalent circuit diagram.

(A) is a schematic diagram of a shared noise killer (SNK) bit line structure and a noise equivalent circuit of the present invention, (b) is a circuit diagram showing a SNK bit line structure of the present invention employing twisted bits;

4 is a view showing a control signal of the SNK bit line structure according to the present invention.

(A) is a bit line signal graph of a folded bit line structure according to the prior art, (b) is a bit line signal graph of a twisted bit structure according to the prior art, and (c) is a SNK bit line structure according to the present invention. (B) is a bit line signal graph of a twisted SNK bit line structure according to the present invention.

(A) of FIG. 6 shows a comparison of the bit line voltage difference when the storage information of the memory cell is " 1 " in the conventional bit line structure and the bit line structure according to the present invention, and (b) shows the storage information of the memory cell. Comparison diagram of the bit line voltage difference when "0".

The present invention relates to a highly integrated dynamic random access memory (DRAM). In particular, the reliability of information sensing when driving a word line is improved by improving bitline coupling noise characteristics, which are expected to be serious in ultra high density (ULSI) DRAM. It relates to a memory array structure of a DRAM for increasing the size of the bit line signal to determine the.

As the cell density of DRAM becomes higher, the gap between bit lines decreases, which leads to a sharp increase in bit line coupling noise generated during the sensing operation. This is the most important problem to consider in circuit design. have.

In order to solve this problem, a twisted bit line structure has recently been developed, which shows an improved noise characteristic compared to the conventional folded bit line structure.

However, the twisted bit line structure is adopted in ULSI class DRAM without any modification because of the problem of area penalty and internal bit line coupling noise caused by cross bit lines. It's hard to do.

A detailed description will be given of a conventional folded bit line structure with reference to FIG. 1.

Typically, the folded bit line is a bit line Bit or BL and a reference bit line Bit- or ) Is manufactured in the same process atmosphere because it is manufactured in the same process atmosphere to minimize the detection noise caused by non-uniform manufacturing method during the process, but as the integration of DRAM increases, the gap between the bit lines decreases rapidly Parasitic capacitance between them increases, causing coupling noise between bit lines.

A coupling capacitor formed between the bit lines of the folded bit structure is formed between an intra bitline coupling capacitor (CBA) formed between bit lines of the same column and bit lines of another column. Comprised of the formed Inter Bitline Coupling Capacitor (CBB), the charge of the memory cell (CS) is transmitted to the bit line capacitor (CBL) by the word line, the charge transferred to the bit line is a reference bit ( The reference bit capacitor (CBA) through the internal bit line capacitor (CBA) and the mutual bit line capacitor (CBB) Reference bit line applied to maintain the precharge voltage Bit line noise is generated as a result of the voltage change of (see FIG. 5A).

As the cross bit line coupling noise and internal bit line coupling noise of the folded bit line structure become serious due to the increase of the density of the memory cells, the noise between the bit lines is canceled by applying the opposite polarity noise to the memory array. A twisted bit structure has been developed and adopted, and the twisted bit line structure will be described in detail with reference to FIG.

The twisted bit line structure includes a bit line BL and a reference bit line ( ) Is a structure in which positions are transposed at regular intervals, and this structure appropriately adjusts the arrangement of odd columns and even columns so that arbitrary bit lines BL and reference bit lines ( By canceling the bit line coupling noise generated in the circuit) by using the bit line coupling noise applied from bit lines of adjacent columns, mutual bit line coupling noise is eliminated.

The capacitance of the mutual bit line coupling capacitor (CBB) of the twisted bit line structure is 1/4 of the capacitance of the internal bit line coupling capacitor (CBA), and the bit lines of the adjacent rows with respect to any bit line (BL1). ( , ) And the reference bit lines BL0 and BL2 cancel the bit line coupling noise.

However, the erasure effect of the bit line noise is limited only to the mutual capacitance of the mutual bit line coupling capacitor CBB by the bit lines of adjacent columns, and the internal bit line coupling capacitance of the capacitor CBA continues to exist as the density increases. Therefore, it is currently emerging as the biggest problem to be solved in ULSI DRAM (see FIG. 5B).

Accordingly, it is an object of the present invention to provide a memory array structure of a DRAM having a bit line structure that reduces the interference between bit lines generated by increasing the memory density and gradually decreasing the distance between the bit lines.

In order to achieve the above object, the present invention proposes a shared noise killer (SNK) bit line structure that eliminates bit line coupling noise generated when driving a word line by using a shared sensing scheme. In order to achieve the above object, the present invention provides a memory array having a shared sensing bit line structure, comprising: a first memory array region (A), a second memory array region (B), and the first and second memories; A plurality of pairs of bit lines BL connected to memory cells in an array area ), And the first and second memory array regions are disposed between a plurality of word lines connected to memory cells and the first and second memory array regions, and are connected between the pair of bit lines to between two bit lines. A plurality of sense amplifiers for sensing and amplifying a voltage difference between the plurality of sense amplifiers, a plurality of P latches connected between each pair of bit lines of the first memory array region, and a plurality of pairs of P latches connected between the pair of bit lines of the first memory array region, A plurality of equalizers for precharging the pair of bit lines at a voltage of 1 / 2VDD according to an equalizer signal, a plurality of N latches connected between each pair of bit lines of the second memory array region, and each bit of the second memory array region A plurality of second equalizers connected between lines to precharge the pair of bit lines with a voltage of 1 / 2VDD according to a second equalizer signal, and the memory array zero Is connected between each pair of bit lines and each of the N latches to select a sensing region between the first and second memory array regions, and selects the first and second control signals VAL and VBL or the third and fourth control signals VAR. And a plurality of barrier transistors for equalizing the bit line voltages of the first and second memory regions in accordance with the pull-up of VBR).

The present invention will now be described in detail with reference to the attached FIGS. 3 and 4.

FIG. 3 (a) shows the SNK bit line structure diagram and the noise equivalent circuit diagram according to the present invention. The SNK bit structure according to the present invention is basically operated by a shared sensing method, and has a single nMOS latch in the A region and B. FIG. The memory cell information of the region can be detected.

Selection of the sensing area for the location of the memory cell is made by MAL (or MAR) and MBL (or MBR), which are barrier MOS, and the operation characteristics of the sensing method are controlled by the SNK bit line structure. With reference to FIG. 4, these items are considered in order of operation.

First, bit lines in areas A and B (refer to (a) in FIG. 3) that maintain voltages of "0" or "ZERO" and "1" or "ONE" in the section <1> of FIG. (Bit or BL) and reference bit line (Bit- or ) Is precharged with a voltage of 1 / 2VDD as equalizer A and equalizer B signals are applied, and MAL (or MAR) and MBL (or MBR), which are barrier MOSs, are controlled signals. VAL (or VAR) and VBL (or VBR) are pulled up to be activated to equalize the bit line voltages of the A and B regions.

After the precharge and equalizing operation is completed, before the word line is driven and the bit line signal is generated, the VBL signal is pulled down in the &lt; 2 &gt; By separating the connected A and B regions, it is possible to prevent the delay of the sensing speed and the reduction of the voltage difference between the bit lines caused by the increased capacitance of the bit lines. At the same time, the VBR signal continues to be pulled up to maintain the connection between the area A and the B of the reference bit line Bit-.

In the section <3> of FIG. 4, a voltage difference is generated between the bit line Bit and the reference bit line Bit- by driving the lead wire. At this time, mutual bit coupling capacitance causing coupling noise by adjacent bit lines is caused. The noise charges transmitted to the reference bit line (Bit-) in the A region by (CBB) and internal bit line coupling capacitance (CBA) are MAR and MBR (resistance in the equivalent circuit diagram), which are barrier MOSs activated by VAR and VBR signals. Bit line coupling cache because it is absorbed by 1 / 2VDD voltage source of area B through RAR and RBR and maintains reference voltage of area A, that is, 1 / 2VDD voltage. The bit line noise caused by the turn is eliminated.

When the voltage difference between the bit line and the reference bit line by the word line driving is applied to the sense amplifier (S / A), the pull-down operation of the bit line is performed by discharging the voltage of the SAN node and driving the N latch in the period <4>. In the section of VDD charging of the SAPA node, the pull-up operation of the bit line through the P latch driving is performed to complete the information detection.

The SNK bit line structure of the present invention described above has a much improved area characteristic compared to the twisted bit line structure because the shared sensing method occupies a minimum area even in the conventional folded bit line structure. It solves the bit line noise problem caused by mutual bit line coupling capacitor and internal bit line coupling capacitor by preventing the floating state of the reference bit line, which is a problem in the detection method of (Fig. 5 (c) and (d). When the twisted bit line structure is adopted as shown in (b) of FIG. 3, the noise characteristics (refer to (a) and (b) of FIG. 6) are improved compared to the SNK bit line structure of the folded bit line. Have

Claims (1)

A memory array having a shared sensing method bit line structure, comprising: a plurality of pairs connected to a first memory array region (A), a second memory array region (B), and memory cells of the first and second memory array regions; Bit line BL ), A plurality of word lines connected to memory cells in the first and second memory array regions, and two bit lines arranged between the first and second memory array regions and connected between the pair of bit lines. A plurality of sense amplifiers for sensing and amplifying a voltage difference therebetween, a plurality of P latches connected between each bit line pair of the first memory array region, and a plurality of P latches connected between each bit line pair of the first memory array region. A plurality of first equalizers for precharging the bit pairs at a voltage of 1 / 2VDD according to a first equalizer signal, a plurality of N latches connected between each pair of bit lines in the second memory array region, and the second memory array A plurality of second equalizers connected between each bit line of an area to precharge the pair of bit lines with a voltage of 1/2 VDD according to a second equalizer signal, and the second memory Connected between each pair of bit lines of the array region and the respective N latches to select a sensing region between the first and second memory array regions, and the first and second control signals VAL and VBL or the third and fourth control signals. And a plurality of barrier transistors for equalizing bit line voltages of the first and second memory regions according to the pull-up of (VAR, VBR).