KR950010477B1 - Non-volatige semiconductor memory device with nand cell - Google Patents

Abstract

The nonvolatile semiconductor memory device with NAND structured cell comprises a row decoder which is shared by at least two memory cell blocks and has first and second pumping circuits shared by at least two memory blocks and connected between string select lines and gate drivers, and a pumping circuit for applying first and second voltages to the gates of the transfer transistors connected to the word lines of the memory cells and the gates of the transfer transistors connected to the gate of the ground select transistor.

Description

Nonvolatile Semiconductor Memory Device With NAND

1 is a block diagram of a conventional low decoder and memory chip.

2 is a partial block diagram of a conventional low decoder and memory chip.

3 is a detailed circuit diagram of a conventional low decoder.

4 is a table showing operation conditions during program / read of a conventional low decoder.

5 is a block diagram of a low decoder and a memory chip according to the present invention.

6 is a partial block diagram of a low decoder and memory chip in accordance with the present invention.

7 is a detailed circuit diagram of a low decoder according to an embodiment of the present invention.

8 is a table showing operation conditions during program / read of the low decoder according to the present invention.

9 is a wordline decoder in accordance with the present invention.

10 is a GSL decoder according to the present invention.

11 is a GSL decoder according to the present invention.

12 is an operation timing diagram according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to an electrically erasable and programmable read only memory device having a page mode.

In order to achieve high integration and low cost of semiconductor memory devices, a NAND flash type Flash Electrically Erasable Programmable Read Onry Memory (EPEROM) has been proposed. In general, a NAND flash memory consists of a predetermined number of memory chips (a unit memory string) connected in series between a string select transistor and a ground select transistor. Simultaneously erased. However, the semiconductor memory device such as the NAND flash type flash memory has a limit in increasing the degree of integration because a row decoder exists in every string pitch. In particular, in a semiconductor memory device having an integration degree of 16 M or more, it is difficult to arrange a low decoder within every string interval. That is, since there is a row decoder that selects each string and row at every string interval, the limit to reduce the memory size is not determined by the limit of the photo etching process but by the size of the row decoder. Is determined.

FIG. 1 is a block diagram of a conventional low decoder and a memory chip, and a 1M NAND flash type EERPOM chip is exemplified. The semiconductor memory device shown in FIG. 1 is composed of left and right memory arrays 10a and 10b each having 1024 x 512 bits of memory rows in a row and a column, respectively. That is, it has a memory of 1024x512x2 bits. Each row 12 has eight floating gate mode transistors and one switching or selection transistor connected in series, and 128 NAND-type memory strings are connected between a corresponding row and a ground line. 128 row decoders 14 are disposed in the center of the memory device to select each row 12 of the left and right memory arrays 10a and 10b.

FIG. 2 is a partial block diagram of a conventional low decoder and a memory chip, and shows a memory array of the memory device shown in FIG. 1 and two low decoders 14 corresponding to the memory array.

3 is a detailed circuit diagram of a low decoder of a conventional NAND flash type EERPOM (Electrically Erasable Programmable Read Only Memory). Is disclosed.

As shown in the figure, the row decoders for selecting rows of the NAND array 10b are enabled only during the program operation with the first and second select gate drivers 16 and 18. The first, second and third pumping circuits 20, 22 and 24 and eight n-channel depletion type transfer transistors T1 to T8 are included. The first and second select gate drivers 16 and 18 are selected by an address decoder which takes address data as input. Meanwhile, the voltages of the control gates CG1 to CG8 are supplied from control gate drivers (not shown) located at the periphery. The control gate voltage is applied to each control gate according to an operation mode and an address selected through a transfer transistor located at the left or right end of the control gate during a program operation.

4 is a table showing a program / read operation condition of the low decoder shown in FIG. A case where the third row of the memory array is selected from FIGS. 3 and 4 will be described as an example.

First, the program operation will be described. During program operation, the input signals Ф _d and Ф _s transition to the 'high' and 'low' states, respectively. Thus, the string select line SSL is selected by the input address and the ground select line GSL is 'low' so that the ground select transistor is turned off. After the selection gate and the first and second nodes N ₁ and N ₂ are charged to a predetermined voltage, the input signal transitions to a 'low' state. The voltages charged in the first and second nodes N ₁ and N ₂ are applied to the gates of the respective transfer transistors so that 18V is transmitted to a word line selected for programming and 10V, which is a program protection voltage, to a non-selected word line. do. Thus, according to the data pattern, '0V'('1' program) or '10V'('0' program) is transmitted to each bit line.

Next, the read operation will be described. During read operation, the input signals Ф _d , Ф _s , and Ф _p transition to the 'high' state, respectively. Ф _r is low. If the selection gate drivers 16 and 18 are selected, the string selection line SSL and the ground selection line GSL are 'high', respectively. Thus, a voltage of 5V is applied to the select gate and the first and second nodes N ₁ and N ₂ are charged up to 5V. The voltages charged in the first and second nodes N ₁ and N ₂ are applied to the gates of the respective transfer gate transistors so that 0.8 V is transmitted to the word line selected for reading and Vcc is transferred to the unselected word lines. Thus, the data stored in each bit line is sensed.

However, the conventional technology has a problem in that a high integration of a semiconductor memory device cannot be realized because its configuration requires connecting a separate low decoder to each array unit (or array array block).

Accordingly, an object of the present invention is to provide a highly integrated semiconductor memory device in a semiconductor memory device.

Another object of the present invention is to provide a NAND type nonvolatile semiconductor memory device in which a high integration due to the area of a low decoder is prevented.

In order to achieve the above object of the present invention, the present invention is characterized in that at least two or more wet array units are nonvolatile semiconductor memory devices sharing one low decoder and a pumping circuit.

According to an embodiment of the present invention, a NAND type nonvolatile semiconductor memory including a plurality of memory pin blocks including a plurality of memory strings including a predetermined number of memory pins connected in series between a string select transistor and a ground select transistor. A device comprising: first and second pumping circuits (40, 44) shared by at least two of said memory buffers and connected between string select lines and string select gate drivers respectively connected to gates of said string select transistors; And a pumping circuit 42 for applying first and second voltages to the gates of the transfer transistors respectively connected to the word lines of the memory cells and the gates of the transfer transistors respectively connected to the gate of the ground selection transistor. The word line is connected to each other and the string Select lines are to be in each of the separated structure, it characterized in that it comprises a row decoder 34 is shared by the two or more memory Cell blocks.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is a block diagram of a low decoder and a memory chip according to the present invention, in which two shock array units (or blocks) in a semiconductor memory device having a shock array arrangement as shown in FIG. 1 include pumping means. It indicates that one low decoder is shared. That is, in the 1-megabit semiconductor memory device, only 64 low decoders are needed because two memory strings share one low decoder including pumping means. Increasing the number of memory strings that share a single row decoder reduces the number of row decoders required.

FIG. 6 is a partial block diagram of a low decoder and a memory chip according to an embodiment of the present invention, and shows that a case in which two ZW array units share a single low decoder including a pumping circuit.

As shown in FIG. 6, the word lines corresponding to the same row are connected to each other, and the string selection lines SSL ₁ and SSL ₂ and the ground selection lines GSL ₁ and GSL ₂ of each array are separated from each other. It is.

FIG. 7 is a detailed circuit diagram of the low decoder of FIG. 6 as a low decoder circuit according to an embodiment of the present invention. As shown in the configuration of FIG. 7, in the present invention, a predetermined program protection voltage is transmitted through a string selection transistor to a string selected from a shared string, and a ground selection transistor to a non-selected string. .

8 is a table showing a program / read operation condition of a memory chip having a shared low decoder according to the present invention.

A case of selecting the third row of the upper array unit of the memory array from FIGS. 7 and 8 will be described as an example.

First, the program operation will be described. It is assumed that data '1' is programmed in the selected first cell and data '0' is programmed in the selected second cell. Input signal during programming Transitions to the 'low' state and the other input signal Ф _p starts to oscillate. When the row decoder is selected by the input row address, the gate of the transfer transistor of the word line and the transfer transistor of the ground select line are charged to a predetermined voltage. Thus, S ₁ -S ₈ and G ₁ -G ₂ are delivered by turning on the transfer transistors. Meanwhile, the string select line SSL ₁ selected by the row address A4 input to the string select gate driver 36 is charged to the first voltage V _pass , and the unselected string select line SSL ₂ becomes 0V. Turn off the unselected string select transistors. The string selection transistor is turned on by the first voltage charged in the selected string selection line SSL ₁ , so that the bit line voltage V ₁ or GND according to the data to be programmed into the string is transferred. Here, 0 V is applied to the bit line of the memory V in which data '1' is to be programmed, and a third voltage V _pi is applied to the bit line of the memory V in which data '0' is to be programmed. On the other hand, the first voltage V _pass is applied to the unselected word line, and a predetermined program voltage, ie, the second voltage V _pgm , is applied to the selected word line. By sharing the low decoder including the pumping circuit with the upper and lower unit, the voltage applied to each word line of the upper array unit is simultaneously applied to the corresponding word line of the lower unit array. . In addition, the selected ground select line GSL ₁ is applied with 0 V to turn off the ground select transistor connected thereto, and the unselected ground select line GSL ₂ is applied with a first voltage V _pass to connect the ground select transistor connected thereto. Turn on The third voltage V _pi , which is a program protection voltage applied to the CSL, is transferred to the bit line of the lower array by the turned on ground selection transistor.

The first memory cell of the array selected by the above operating conditions is applied with a second voltage (V _pgm ) and a voltage of 0V to the gate and the drain, respectively, so that tunneling of electrons from the semiconductor substrate to the floating gate occurs. You have 1 'of data. On the other hand, the first and second voltages V _pass and 0V are applied to the gates and the drains of the remaining cells in the selected string, respectively, thereby preventing program operation. In addition, since the second voltage V _pgm and the third voltage V _pi are respectively applied to the gate and the drain of the selected upper wafer array, tunneling of electrons from the substrate to the floating gate does not occur, thereby pre-programming erase operations. The negative threshold voltage, i.e., '0' data, is maintained. On the other hand, the first voltage V _pass and the third voltage V _pi are applied to the gates and the drains of the remaining cells in the selected string, respectively, so that no program operation occurs. At this time, the string select transistor of the unselected lower end array unit is turned off by a voltage of 0V applied to the string select line, and the ground select transistor is turned on by a first voltage V _pass applied to the ground select line and is not selected. The third voltage V _pi delivered through CSL is applied to the sources and drains of all charges in the string. Thus, all books in the unselected string are not programmed.

The following describes the 'lead' operation.

As shown in FIG. 8, in the read operation The signal transitions to the 'high' state and the Ф _p signal does not oscillate. When the row decoder including the pumping circuit is selected by the input row address, S _1- S ₈ and G _1- G ₂ are transferred by applying the Vcc voltage to the gates of the word line transfer transistor and the ground transfer transistor. At this time, the voltage delivered to the selected row is 0V and the voltage delivered to the unselected row is Vcc. Thus unselected pins act as transfer transistors. At this time, CSL becomes 0V and serves as ground. The string selection line selected by the row address becomes Vcc and the unselected string selection line becomes 0V to select one string among the shared strings.

9 is an embodiment of a word line decoder according to the present invention, and S1, S2,... , Supply the S8 signal.

FIG. 10 is an embodiment of a GSL decoder according to the present invention. In FIG. 7, the signals G1 and G2 connected to the ground selection lines GSL1 and GSL2 are supplied.

FIG. 11 is an embodiment of a CSL decoder according to the present invention, and FIG. 7 supplies a CSL signal connected to a column select line in FIG.

12 is an operation timing diagram according to the present invention. In the twelfth degree ? T, which represents the time interval until the signal is enabled, is determined by the chip internal circuit. In addition, the voltage level of the V _pgm and V _pi signals rises above the power supply voltage Vcc level easily by an internal boosting circuit known in the art.

5 is a configuration realized based on the technical idea of the present invention, and the specific circuit for realizing the same is not limited to the above-described FIGS. 6 to 11 but it is obvious to those skilled in the art that there are various other aspects. It is true.

As described above, according to the present invention, in the NAND flash type EERPOM memory device, a plurality of shock array units share a single low decoder including a pumping circuit, so that the bit size in the bit line direction is not limited by the low decoder size. There is an effect that can be greatly reduced. As a result, the limit of shrinkage size is determined by the limitation of the photolithography process, thereby facilitating the implementation of a highly integrated semiconductor memory device.

Claims (3)

11. A NAND type nonvolatile semiconductor memory device comprising a plurality of memory pin blocks comprising a plurality of memory strings comprising a predetermined number of memory pins connected in series between a string select transistor and a ground select transistor; First and second pumping circuits 40 and 44 and shared by at least two or more memory check blocks, respectively, connected between string select lines and string select gate drivers connected to gates of the string select transistors. And a pumping circuit 42 for applying first and second voltages to the gates of the transfer transistors respectively connected to the word line and the gates of the transfer transistors respectively connected to the gate of the ground selection transistor. And a row decoder (34) shared by the two or more memory blocks to allow the string selection lines to be connected to each other and to form a separate structure. The NAND type nonvolatile semiconductor memory device according to claim 1, wherein the NAND type nonvolatile semiconductor memory device is ERPOM, which is electrically erasable and programmable. The NAND type nonvolatile semiconductor memory of claim 1, wherein a predetermined program protection voltage is transmitted through the string selection transistor to a string selected from a shared string and through the ground selection transistor to a non-selected string. Device.