KR950010447A - V.C.1 (VC1) Signal Delay Device - Google Patents

Abstract

In the present invention, the synchronous digital multi-transmitter synchronizes the DS1-class dependent signal to the device and performs a test on the VC1 transmission path based on the loopback function of the device by using a pseudo conversion (PRBS) signal generation function implemented in the circuit. When the LOT (Lossog Tributary) of the DS1 signal is detected, the VC1 transmission path is maintained by mapping a signal of always "1" (ALL "1" signal) to the payload of the VC1. It is an object of the present invention to provide a VC1 signal-imaging device, which is capable of providing an OR device A 110, an OR device B 120, a selector A 210, a selector B 220, and a PRBS / ALL-ONE signal generator 300. ), An ALL-ONE detector and a line signal decoder 400, a PRBS detector 500, an 8-bit asynchronous buffer 600, a 64-stage buffer and a phase comparator 700.

Description

V.C.1 (VC1) Signal Delay Device

Since this is an open matter, no full text was included.

1 is a circuit diagram of the present invention.

Claims (5)

ORing the LOT (Lossog Tributary) provided by the LIU (Lime Interqace Unit) for receiving the external DS1 signal and CPULOT, a signal used for testing by an external CPU module to perform the CPU function. A first logical sum (OR) processing means 110 for generating one signal (ORA) 13, a loopback signal CPULBA from a CPU module, and an output signal ORA from the first logical sum processing means 110; The second logic sum processing means 120 for generating the ORB signal and the LO, which is an externally oscillating clock (1.544 MHz or 2.048 MHz) with high accuracy provided from the outside, are received. Receives the output of the 1 logical sum processing unit 110 and generates a PBS signal and a PB-ONE signal having a pseudo-transformation (PRBS) signal corresponding to the speed of the corresponding DS1-class signal and a signal of always 1 (ALL_ONE). PRBS / ALL-ONE signal generating means 300 and the receiving anode provided recovered from the external LIU The received NRZ (RNRZ) signal 15 is inputted by receiving the RPOS signal 5, the received negative signal RNEG signal 6, and the received clock RCLK 7, and decoding the line signal and performing the AIS signal detection function. And ALL_ONE detection and line signal decoding means 400 for generating the CPU monitoring information (CPUMON signal; 16), and the output signals PB-ONE 14 and ALL of the PRBS / ALL-ONE signal generating means 300. The output signal (RNRZ) 15 of the -ONE detection and line signal decoding means 400 is selected according to the state (low or high) of the output signal ORB (17) of the second logical sum processing means 120. A first selection means 210 for generating an output signal (selection A; 18) to be a payload of RRCZ 15 from the ALL-ONE detection and line signal decoding means 400 and a RCLK from LIU; 7) and a transmit NRZ signal (TNRZ signal provided from an external DS1 signal transmission function); 10) PRBS signal detection function is executed based on CPU loopback signal B (CPULBB signal; 8), which is the loopback signal provided from CPU module, by receiving the transmission clock (TCLK; 9) and bit error occurred in PRBS signal. Is detected, the PRBS detection means 500 which generates an error signal PRBSERR 16, the selection A signal 18 which is the VC1 payload from the first selection means 600, the buffer WCK 37, S1 / The 8-stage data and the 8-stage write address most significant bit (8WMSB) by performing the function of the 8-stage asynchronous buffer by receiving the S2 state (Cont) 23, the buffer reset 24, and the intermediate frequency 19 supplied from the outside. 21) and an 8-bit asynchronous buffer means 600 for generating an 8-bit read address most significant bit (8RMSB; 22) signal, and the 8-speed data 20 from the first selection means 600 are externally provided. Second selection means 220 for selecting according to the buffer selection signal 11 and generating a selection NRZ signal 25; Third logical sum processing means 130 for receiving the buffer selection signal 11 and the synchronous mode signal 12 from the logic sum processing and outputting the synchronous buffer signal 26, and RCLK (7) and LO (4) from the outside. ), A power reset (PWRST; 25), a system clock (49), a CPU reset (CPURST; 27), and a V5 timing signal 30 are inputted, and the ORB signal 17 is received from the second logical sum processing means 120. The 8-bit asynchronous buffer receiving the selected NRZ signal 25 from the second selecting means 220 and receiving the 8-WMSB 21 and 8-RMSB signals from the 8-bit asynchronous buffer means 600. Means 600 provides buffer WCK 37, S1 / S2 Cont. 23, buffer reset 24 signals, and sends data 28 and buffer status detection signals (CPU-VD / PV signals; 29). VC1 signal mapping circuit comprising a 64-stage buffer for outputting and a phase comparison means (700). According to claim 1, wherein the PRBS / ALL-ONE signal generating means 300, PRBS for generating a PRBS signal corresponding to the DS1 class signal rate using an externally supplied DS1 class self-oscillating clock (LO; 4) The PRBS generator 310 using a generator 310, an ALL-ONE generator 320 that simply outputs high, and an output signal ORA 13 of the first logical sum processing means 110. And a second selecting means 330 for outputting the PB-ONE 14 signal to the first selecting means 210 by selecting one of the outputs of the ALL-ONE generator 320. VC1 signal mapping circuit. The method of claim 1, wherein the PRBS detecting means 500 receives the RCLK (7) and TCLK (9) to selectively output the CLK (35) using the CPUBB (8) signal provided from an external CPU module Fifth selecting means 520 which receives the fourth selecting means 510 and the RNRZ 15 and the TNRZ 16 and selectively outputs the NRZ 36 using the CPULBB 8 signal provided from an external CPU module; And the CLBS 35 and the NRZ 36, which are outputs of the third and fourth selection means 510 and 520, perform a PRBS detection function corresponding to the PRBS signal selected according to the type of the DS1 level signal. And a PRBS detection circuit (530) for supplying an error signal (PRBSERR) 16 to the CPU module when a bit error is included in the signal. The 8-bit asynchronous buffer means 600 receives a buffer WCK signal output from the 64-step buffer and the phase comparator 700, and writes the address 8WAD 38 and the most significant bit 8WMSB. Gaps the system clock 19 according to the state of the S1 / S2Cont. 23 signal by receiving the write address 620 and the intermediate frequency 19 and the S1 / S2Cont. a clock gapping device 640 generating a read clock 8RDCK 40 by a gapping operation, and a read address 8RAD 39 and a most significant bit received from a clock gapping device 640 and a read clock 8RDCK 40 provided by the clock generator 640. In the read addresser 630 for outputting (8RMSB; 22), the read and write addresses which are outputs of the write addresser 620 and the read addresser 630, and the 64-stage buffer and phase comparison means 700. Receives a buffer WCK signal, which is a provided write clock, and writes selection A 18 which is an output means of the first selection means 210. An VC1 signal mapping circuit comprising an 8-bit asynchronous buffer 610 for writing an address based on the address. 2. The 64-bit buffer and phase comparing means 700 reads the write address most significant bit (WMSB) and reads using the sync buffer signal 26, which is an output signal of the third logical sum processing means 130. S1 / S2 Cont by comparing the write address value and the read address value by receiving the outputs of the third and fourth selection means 790 and 792 for selecting the most significant bit (RMSB) and the outputs of the third and fourth selection means 790 and 792. (23) a gap comparator 791 for outputting a signal and a system clock 49 inputted by using an S1 / S2 Cont. 23 signal, which is an output of the phase comparator 791, are output by gapping them A buffer WCK (37) which is an output signal by selecting LO (4) and RCLK (7) input based on an ORB (17) signal which is an output of the second logical sum processing means (120) and the clock gapping device (780). A third selection means 720 for supplying a signal and a buffer WCK signal 37 which is an output of the third selection means 720, and outputs a write address 64WMSB; A read addresser 750 for receiving a write addresser 730, an output signal 64RDCK of the clock gapping device 780, and outputting a read address 64RAD 42; and the second selection means 220; A 64-stage buffer 710 which receives the selection NRZ 25 which is an output signal of the output signal according to the write address which is the output of the write address device 730 and outputs the output signal according to the read address that is the output of the read address device 750; UD / to detect under-run and over-run in the 64-stage buffer 710 and notify the CPU module through a CUP-UD / OV 29 signal when a situation occurs. OR detector 740, fourth logical sum processing means 760 for ORing and outputting power reset signal PWRST; 25 and CPU reset signal CPURESET 27; and fourth logical sum processing means. And an automatic reset unit 770 which receives the output of 760 and the V5 timing signal and automatically outputs a reset signal. VC1 signal mapping circuit. ※ Note: The disclosure is based on the initial application.