KR950010240Y1 - The comb filter circuit for increasing the sensitivity of seperating y.c. signals - Google Patents

The comb filter circuit for increasing the sensitivity of seperating y.c. signals Download PDF

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KR950010240Y1
KR950010240Y1 KR2019900014668U KR900014668U KR950010240Y1 KR 950010240 Y1 KR950010240 Y1 KR 950010240Y1 KR 2019900014668 U KR2019900014668 U KR 2019900014668U KR 900014668 U KR900014668 U KR 900014668U KR 950010240 Y1 KR950010240 Y1 KR 950010240Y1
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signal
resistor
inverting terminal
output
operational amplifier
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KR920007307U (en
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김응조
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대우전자 주식회사
김용원
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/77—Circuits for processing the brightness signal and the chrominance signal relative to each other, e.g. adjusting the phase of the brightness signal relative to the colour signal, correcting differential gain or differential phase
    • H04N9/78—Circuits for processing the brightness signal and the chrominance signal relative to each other, e.g. adjusting the phase of the brightness signal relative to the colour signal, correcting differential gain or differential phase for separating the brightness signal or the chrominance signal from the colour television signal, e.g. using comb filter
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1207—Resistor

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Processing Of Color Television Signals (AREA)

Abstract

내용 없음.No content.

Description

Y.C분리감도를 증가시킨 콤필터(COMB FILTER)회로COMB filter circuit with increased Y.C separation sensitivity

제1도는 본 고안의 회로도이다.1 is a circuit diagram of the present invention.

제2도는 본 고안을 설명하기 위한 각부의 파형도이다.2 is a waveform diagram of each part for explaining the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

INV : 인버터 OP1 : 차동증폭기INV: Inverter OP1: Differential Amplifier

OP2,OP3 : 연산증폭기 R1-R12 : 저항OP2, OP3: Operational Amplifier R1-R12: Resistance

본 고안은 칼라수상기 화면의 노이즈 제거회로 즉 해상도 증가회로 관한 것으로, 특히 딜레이회로와 연산증폭기를 이용하여 Y(휘도)신호와 C(칼라)신호의 분리감도를 증가시키므로써 칼라수상기 화면의 선명도를 증가시키고자 한 Y.C분리 감도를 증가시킨 콤필터 회로에 관한 것이다.The present invention relates to a noise removing circuit of a color receiver screen, that is, a resolution increasing circuit. In particular, the sensitivity of the Y (brightness) signal and the C (color) signal is increased by using a delay circuit and an operational amplifier. A comb filter circuit having increased YC separation sensitivity to increase.

일반적으로, 디엠퍼시스(Deemphasis)된 Y신호와 C신호가 그대로 출력될 경우에는, Y신호와 C신호가 중첩되어 3.5㎒ 분근에서 잡음 성분으로 칼라수상기 화면에 노이즈로 나타나기 때문에 디엠퍼시스된 Y신호와 C신호의 잡음을 제거하여 줄 필요가 있었다.In general, when a de-emphasized Y signal and a C signal are output as they are, since the Y signal and the C signal overlap and appear as noise on the color receiver screen as noise components in the 3.5 MHz root, the de-emphasized Y signal and It was necessary to remove the noise of the C signal.

종래의 경우 상기와 같은 Y신호와 C신호의 중첩으로 인한 잡음을 제거하기 위하여, 디엠퍼시스된 Y신호와 C신호가 고역필터를 통하여 잡음성분만이 추출되며, 추출된 잡음성분이 리미터의 인버터를 통하여 진폭이 제한되고, 위상이 90˚반전된 후 디엠퍼시스된 Y신호와 C신호가 합성되므로써 잡음성분이 90°반전된 잡음에 의해 상쇄되도록 구성하였으나, 이는 외관상 잡음제거 비율이 높아질뿐 화상 상승부분의 잡음은 제거되지 않기 때문에 입력신호가 좋지 못할 때에는 화상윤곽부분의 잡음은 제거되지 못하여 3.5㎒ 부근에서는 Y신호가 C신호로 인식되어져 잡음이 여전히 남아있게 되는 문제점이 있었다.In the conventional case, in order to remove noise due to the overlap of the Y signal and the C signal as described above, only the noise component is extracted from the de-emphasized Y signal and the C signal through a high pass filter, and the extracted noise component is applied to the inverter of the limiter. Although the amplitude is limited and the phase is reversed by 90 °, the de-emphasized Y signal and C signal are synthesized so that the noise component is canceled by the noise inverted by 90 °. Since the noise is not removed, when the input signal is not good, the noise at the edge of the image cannot be removed and the Y signal is recognized as the C signal in the vicinity of 3.5 MHz, so that the noise remains.

이에 본 고안은 상기와 같은 문제점을 해소하기 위하여 안출한 것으로, 1H지연회로 및 차동증폭기와 연산증폭기를 사용하여 평상시의 Y신호 및 C신호의 잡음성분을 제거함은 물론, 입력신호가 좋지 않을 경우에 발생하는 화상의 윤곽부분의 잡음을 제거함과 동시에 Y신호와 C신호를 완전히 분리하여 3.58MHz 부근에서 발생되는 잡음을 분리하여 순수한 Y신호와 C신호를 추출하여 선명한 화면 즉 고해상도의 화면을 얻도록 함을 목적으로 한 것이다.Therefore, the present invention has been devised to solve the above problems, by using a 1H delay circuit, a differential amplifier, and an operational amplifier to remove the noise components of the usual Y signal and the C signal, as well as when the input signal is not good. At the same time, it removes the noise of the contour part of the generated image and at the same time completely separates the Y signal and the C signal to separate the noise generated around 3.58MHz to extract the pure Y signal and the C signal to obtain a clear screen or high resolution screen. It is for the purpose.

상기와 같은 목적을 달성하기 위한 본 고안의 구성을 첨부된 도면 제1도 및 제2도를 참고로 하여 설명하면 다음과 같다.The configuration of the present invention for achieving the above object will be described with reference to the accompanying drawings, FIGS. 1 and 2 as follows.

제1도는 본 고안의 회로도로써, 미도시된 증폭기로부터 디엠퍼시스된 입력신호(Y+C)가 저항(R2) 및 저항(R10)을 거쳐 차동증폭기(OP1)의 비반전단자(+)와 연산증폭기(OP3)의 반전단자(-)에 각각 연결됨과 동시에 딜레이회로(DELAY)에 인가되도록 연결하고, 상기 딜레이회로(DELAY)의 출력을 저항(R1)을 거쳐 차동증폭기(OP1)의 반전단자(-)에 인가되도록 함과 동시에 저항(R6)을 거쳐 연산증폭기(OP2)의 반전단자(-)에 인가되도록 연결하고, 상기 차동증폭기(OP1)의 비반전단자(+)에는 상기 저항(R2)과 일측접지된 저항(R4)을 공통연결함과 동시에 반전단자(-)와 상기 차동증폭기(OP1)의 출력단 사이에 저항(R3)을 연결하되 상기 차동증폭기(OP1)의 출력은 저항(R5)을 거쳐연산증폭기(OP2)의 반전단자(-)에 인가되도록 상기 저항(R6)과 공통 연결하고, 상기 연산증폭기(OP2)의 비반전단자(+)는 저항(R8)을 통해 접지함과 동시에 그의 반전단자(-)와 출력단 사이에 저항(R7)을 연결하되 상기 연산증폭기(OP2)의 출력이 인버터(INV) 및 저항(R9)을 거쳐 연산증폭기(OP3)에 연결하고, 상기 연산증폭기(OP3)의 비반전단자(+)는 저항(R12)을 통해 접지한 후 상기 연산증폭기(OP3)의 반전단자(-)와 출력단 사이에 저항(R11)을 연결하고, 상기 각 연산증폭기(OP2)(OP3) 의 출력단으로부터 Y신호 및 C신호를 얻음으로써 구성되어진다.FIG. 1 is a circuit diagram of the present invention, in which an input signal Y + C de-emphasized from an amplifier (not shown) is calculated with a non-inverting terminal (+) of a differential amplifier OP1 via a resistor R2 and a resistor R10. It is connected to the inverting terminal (-) of the amplifier OP3 and connected to be applied to the delay circuit DELAY, respectively, and the inverting terminal of the differential amplifier OP1 via the resistor R1 via the resistor R1. -) And at the same time through the resistor (R6) connected to the inverting terminal (-) of the operational amplifier (OP2), the non-inverting terminal (+) of the differential amplifier (OP1) to the resistor (R2) And the one-side grounded resistor (R4) in common and at the same time connect the resistor (R3) between the inverting terminal (-) and the output terminal of the differential amplifier (OP1), the output of the differential amplifier (OP1) is a resistor (R5) Common connection with the resistor (R6) to be applied to the inverting terminal (-) of the operational amplifier (OP2) through, and the non-inverted terminal of the operational amplifier (OP2) (+) Is grounded through resistor R8 and at the same time the resistor R7 is connected between its inverting terminal (-) and the output terminal, and the output of the operational amplifier OP2 is connected to the inverter INV and resistor R9. The non-inverting terminal (+) of the operational amplifier OP3 is grounded through a resistor R12, and then the resistance between the inverting terminal (-) and the output terminal of the operational amplifier OP3. (R11) is connected, and a Y signal and a C signal are obtained from the output terminals of the respective operational amplifiers OP2 and OP3.

상기와 같이 구성된 본 고안을 제2도의 파형도를 참고로 하고 작용 및 효과에 의거하여 좀 더 상세히 설명하면 다음과 같다.Referring to the present invention configured as described above with reference to the waveform diagram of Figure 2 and described in more detail based on the action and effect as follows.

제2도의 파형(①)에서 보여지는 바와 같이 복합영상 신호는 C신호 및 Y신호와 동기신호로 구성되며, 3.58㎒의 C신호는 Y신호의 각레벨에 실려 전송이 된다. 이때 공교롭게도 파형(①)의 a와 같은 3.58㎒에 인접하는 주파수위 Y신호가 발생할 경우 상기 Y신호가 C신호로 인식되어지는 문제가 발생한다. 본 고안은 이와 같은 C신호로 잘못 인식되어진 Y신호를 제거하기 위한 것이다.As shown by the waveform 1 of FIG. 2, the composite video signal is composed of a C signal and a Y signal and a synchronization signal, and the C signal of 3.58 MHz is carried on each level of the Y signal and transmitted. In this case, when the Y signal on the frequency adjacent to 3.58 MHz, such as a of the waveform ①, occurs, the Y signal is recognized as a C signal. The present invention is intended to remove the Y signal that was incorrectly recognized as such a C signal.

즉 미도시된 증폭기에 의해 디엠퍼시스된 신호(Y+C) 파형(①)이 인가되면 딜레이회로(DELAY)에 의해 1H 딜레이됨과 동시에 3.58㎒의 칼라신호 성분만이 분리되어 출력되는데 이때 분리되어 출력된 파형이 제2도의 파형(②)에서 보여진다.That is, when the signal (Y + C) waveform (①) de-emphasized by the amplifier (not shown) is applied, the 1H delay is delayed by the delay circuit DELAY, and only 3.58MHz color signal components are separated and output. The waveform is shown in the waveform ② of FIG.

상기 1H딜레이됨과 동시에 주파수 필터링된 C신호파형(②)은 차동증폭기(OP1)및 연산증폭기(OP2)의 반전단자(-)에 각각 입력되며, 그와 동시에 신호 입력단에는 그 다음 신호(Y+C)가 입력되는데 이때 입력되는 C신호는 방송신호 전송률에 따라 종전의 C신호와 180˚위상차를 갖게 된다. 즉, 이때 입력되는 신호(Y+C)의 파형은 파형(①)과 C신호의 위상만 반전되었을뿐 동일한 신호 파형을 이룬다.The 1H delayed and frequency filtered C signal waveform (②) is input to the inverting terminal (-) of the differential amplifier OP1 and the operational amplifier OP2, respectively, and at the same time, the next signal (Y + C) at the signal input terminal. In this case, the input C signal has a 180 ° phase difference from the previous C signal according to the broadcast signal transmission rate. That is, the waveform of the input signal (Y + C) at this time forms the same signal waveform only the phase of the waveform (1) and the C signal is inverted.

상기 입력된 C신호만이 180˚위상이 반전된 신호(Y+C)는 차동증폭기(OP1)의 비반전단자(+)와 연산증폭기(OP3)의 반전단자(-)에 입력되며, 차동증폭기(OP1)에 입력된 각 신호는 차분증폭되어 출력되는데 이때 출력되는 신호는 파형(③)과 같다. 즉, 뒤이어 입력된 신호(Y+C)에 의해 3.58㎒의 Y신호가 제거된다.The signal Y + C whose 180 ° phase is inverted only by the input C signal is input to the non-inverting terminal (+) of the differential amplifier OP1 and the inverting terminal (-) of the operational amplifier OP3, and the differential amplifier Each signal input to (OP1) is differentially amplified and output, and the output signal is the same as the waveform (③). That is, the Y signal of 3.58 MHz is removed by the subsequent input signal Y + C.

상기 차동증폭기(OP1)을 통해 출력된 신호파형(③)은 저항(R5)를 통해 1H딜레이된 신호파형(②)와 합쳐져 연산증폭기(OP2)의 반전단자에 인가되어 '1/2(Y+2C)-C'로 연산증폭된 후 출력되는데, 이때 출력되는 신호파형은 파형(④)와 같은 순수한 Y신호만으로 분리되어 출력된다.The signal waveform ③ outputted through the differential amplifier OP1 is combined with the signal waveform ② delayed by the 1H delay through the resistor R5 and applied to the inverting terminal of the operational amplifier OP2 to provide '1/2 (Y +'). 2C) -C 'is output after the operation amplified, the output signal waveform is separated into a pure Y signal, such as the waveform (④) is output.

또한 상기 연산증폭기(OP2)로부터 출력된 신호(④)는 인버터(INV.)에 의해 반전된 후 저항(R9)를 거쳐, C신호만이 180˚반전된 신호(Y+C)와 합쳐져서 연산증폭기(OP3)의 반전단자에 인가되어 '(Y+C)-Y'로 연산된 후 증폭되어 출력되는데, 이때 출력되는 신호는 파형(⑤)에서 보여지는 바와같이 잘못인식될 신호(a)가 제거된 순수한 C신호만이 출력된다.In addition, the signal ④ output from the operational amplifier OP2 is inverted by the inverter INV. And then passed through the resistor R9, and only the C signal is combined with the signal Y + C inverted by 180 °. It is applied to the inverting terminal of (OP3), it is calculated as '(Y + C) -Y', and then amplified and output. At this time, the signal to be misrecognized as shown in waveform (⑤) is removed. Pure C signal is output.

상기에서 설명한 바와같이 본 고안은 종래의 3.58㎒ 부근의 Y신호가 C신호로 잘못 인식되어져 잡음성분 즉 노이즈로 작용하여 칼라 수상기 화면의 영상에 영향을 주어 깨끗하고 선명한 화면의 제공하지 못했던 문제점을 해결하여 3.58㎒ 부근에서도 순수한 Y신호와 C신호를 얻을 수 있도록 하므로써 밝고 선명한 영상을 얻을수 있도록 하는 효과가 있다.As described above, the present invention solves the problem of failing to provide a clean and clear screen by affecting the image of the color receiver screen by acting as a noise component, that is, the Y signal is incorrectly recognized as a C signal. Therefore, the pure Y and C signals can be obtained in the vicinity of 3.58MHz, so that bright and clear images can be obtained.

Claims (1)

(정정) 증폭기로부터 디엠퍼시스된 입력신호(Y+C)가 저항(R2) 및 저항(R10)을 거쳐 차동증폭기(OP1)의 비반전단자(+)와 연산증폭기(OP3)의 반전단자(-)에 각각 연결됨과 동시에 딜레이회로(DELAY)에 인가되도록 연결하고, 상기 딜레이회로(DELAY)의 출력을 저항(R1)을 거쳐 차동증폭기(OP1)의 반전단자(-)에 인가되도록 함과 동시에 저항(R6)을 거쳐 연산증폭기(OP2)의 반전단자(-)에 인가되도록 연결하고, 상기 차동증폭기(OP1)의 비반전단자(+)에는 상기 저항(R2)과 일측접지된 저항(R4)을 공통연결함과 동시에 반전단자(-)와 상기 차동증폭기(OP1)의 출력된 사이에 저항(R3)을 연결하되 상기 차동증폭기(OP1)의 출력은 저항(R5)을 거쳐 연산증폭기(OP2)의 반전단자(-)에 인가되도록 상기 저항(R6)과 공통 연결하고, 상기 연산증폭기(OP2)의 비반전단자(+)는 저항(R8)을 통해 접지함과 동시에 그의 반전단자(-)와 출력단 사이에 저항(R7)을 연결하되 상기 연산증폭기(OP2)의 출력이 인버터(INV) 및 저항(R9)을 거쳐 연산증폭기(OP3)에 연결하고, 상기 연산증폭기(OP3)의 비반전단자(+)는 저항(R12)을 통해 접지한 후 상기 연산증폭기(OP3)의 반전단자(-)와 출력단 사이에 저항(R11)을 연결하고, 상기 각 연산증폭기(OP2)(OP3)의 출력단으로 부터 Y신호 및 C신호를 얻음으로써 구성되는 Y.C분리감도를 증가시킨 콤필터 회로.The input signal (Y + C) de-emphasized from the (correction) amplifier passes through the resistor (R2) and resistor (R10) and the non-inverting terminal (+) of the differential amplifier (OP1) and the inverting terminal (-) of the operational amplifier (OP3). Are connected to the delay circuit DELAY, and the output of the delay circuit DELAY is applied to the inverting terminal (-) of the differential amplifier OP1 through the resistor R1. Connect to the inverting terminal (-) of the operational amplifier OP2 via (R6), the non-inverting terminal (+) of the differential amplifier (OP1) is connected to the resistor (R2) and one side grounded resistor (R4) At the same time, the resistor R3 is connected between the inverting terminal (-) and the output of the differential amplifier OP1 and the output of the differential amplifier OP1 is connected to the operational amplifier OP2 through the resistor R5. Common connection with the resistor (R6) to be applied to the inverting terminal (-), the non-inverting terminal (+) of the operational amplifier (OP2) is the same as the ground through the resistor (R8) Connect a resistor (R7) between its inverting terminal (-) and an output terminal at the same time, and the output of the operational amplifier (OP2) is connected to the operational amplifier (OP3) via an inverter (INV) and a resistor (R 9 ), and The non-inverting terminal (+) of the operational amplifier OP3 is grounded through the resistor R12, and then connects the resistor R11 between the inverting terminal (-) and the output terminal of the operational amplifier OP3, and each of the operational amplifiers A comb filter circuit having increased YC separation sensitivity, which is constructed by obtaining Y and C signals from the output of (OP2) (OP3).
KR2019900014668U 1990-09-22 1990-09-22 The comb filter circuit for increasing the sensitivity of seperating y.c. signals KR950010240Y1 (en)

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KR2019900014668U KR950010240Y1 (en) 1990-09-22 1990-09-22 The comb filter circuit for increasing the sensitivity of seperating y.c. signals

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KR2019900014668U KR950010240Y1 (en) 1990-09-22 1990-09-22 The comb filter circuit for increasing the sensitivity of seperating y.c. signals

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KR950010240Y1 true KR950010240Y1 (en) 1995-12-04

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