KR950009741Y1 - Auto detection circuit for vcr tape velosity - Google Patents

Abstract

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Description

Regeneration tape speed automatic discrimination circuit in VCR.

1 is a block diagram of the present invention

2 is a detailed circuit diagram of the present invention.

(A)-(T) of FIG. 3 (a), (b) is an operation waveform diagram of the circuit of this invention.

* Explanation of symbols for main parts of the drawings

1: Reset and discrimination data transmission clock generator 2: Multiplication unit

3: Counter 4: Discrimination Data Transmitter

FF1-FF14: flip-flop G1-G16: NAND gate

GN1-GN9: Noah gate NR1-NR9: Inverter

The present invention relates to an automatic tape speed discrimination circuit in a VCR. In particular, the tape recording speed in a VCR is able to automatically determine the recording state of a tape using a capstan frequency oscillator (CFG) and a control pulse (CTL) cycle. It relates to an automatic discrimination circuit.

Conventional VCRs are not equipped with a circuit for determining the speed of the playback tape, and thus there is a problem that the mode recorded on the tape cannot be determined and the playback speed can not be determined accordingly.

The present invention was devised to solve such a conventional problem. The VCR includes a reset and discriminant data transmission clock generator, a multiplier unit, a counter, and a discriminant data transmission unit to monitor the recording state of the tape. It is an object of the present invention to provide a circuit for automatically determining the speed of reproducing tape in a VCR, which can be easily operated by using the VCR by automatically determining the speed of the reproducing tape using the period of. The present invention is described in detail as follows.

As shown in FIG. 1 and FIG. 2, the configuration of the present invention is a reset and discrimination data transmission clock for generating a clock signal for resetting or transmitting discrimination data according to the control pulse (CTL) and clock pulse states. The generator 1, a multiplier 2 for multiplying the signal CFG output from the capstan frequency oscillator, and a signal output from the multiplier 2 are counted to become a reference value for mode discrimination. A counter 3 outputted to the discrimination data transmission section 4 and reset by an output of the reset and discrimination data clock generator 1, and output terminals 01 and 02 of the counter 3; And a discrimination data transmission unit 4 for decoding the signal state and determining the mode discrimination data as a result and outputting a mode discrimination signal corresponding to a predetermined speed (high speed, standard speed, and low speed). Where CTL = 30Hz, SP mode CFG = 720Hz, CFG = 360Hz in LP mode, CFG = 240Hz in EP mode, 2 multiplying unit (2), counter (3) are implemented with 31 binary counter and high speed (EP) when the count value is '20' The high speed signal is output through its output stage (01), and when the count value is '31', the standard speed (LP) and the low speed (SP) are distinguished. Judging by the count value, it was configured to output 'high' through its output terminal (02).

In addition, the reset and discrimination data transmission clock generator 1 mutually interacts with a plurality of de-flop flops FF1-FF3, NAND gates G1.G2, NOR gates GN4, and inverters NR1.NR2. The two multiplying parts 2 are made by connecting the flip-flops FF4 and FF5 and the plurality of NOR gates GN1-GN3 to each other, and the 31 binary counter 3 The flip-flop (FF6-.FF10), the NAND gates (G3-G5, G8), the NOR gates (GN5, GN6), and the inverter (NR3-NR5) are interconnected to each other, and the discrimination data transmitter (4) ) Is formed by interconnecting a plurality of flip-flops (FF11-FF14), NAND gates (G6, G7, G9-G16), NOR gates (GN7-GN9) and inverters (NR6-NR9).

Referring to the effect of the present invention configured as described with reference to Figure 3 (A)-(T) as follows.

First, a 30 Hz control pulse such as (B) of FIG. 3 reproduced on the tape is inverted as shown in (C) of FIG. 3 through the inverter NR1 and input to the clock terminal CK of the flip-flop FF1. At the falling edge, its output terminal Ql signal becomes 'high' as shown in FIG. 3D and is applied to the input terminal D of the flip-flop FF2.

Therefore, the output terminal Q2 signal of the flip-flop FF2, to which the predetermined clock signal (that is, the clock signal such as (A) of FIG. 3) is input to the clock terminal CK, is in the same state as that of (E) of FIG. Therefore, the output terminal Q3 of the flip-flop FF3 is output with a delayed period from one cycle of the clock signal as shown in FIG.

In this case, since the 'high' signal is applied to the reset terminal R of the de-flop flop FF1 as the output terminal Q3 of the de-flop flop FF3 becomes 'high' The output terminal Ql signal of the flop FFl becomes 'low' and is applied to the input terminal D of the dip-flop flop FF2, so that the output terminal Q2 becomes 'low' to its output terminal Q2, so that the input of the flip-flop FF2 is input. Since it is applied to the terminal D, its output terminal Q2 is also 'low', and the output terminal Q3 of the deflip-flop FF3 remains 'low' until the next control pulse CTL is input 'high'. Will be maintained.

At this time, the output terminal Q2 of the flip-flop FF2 is applied to one input terminal of the NAND gate G2 and is inverted as shown in FIG. 3 (G) through the inverter NR2 and the NAND gate Gl and NOR. It is applied to one input terminal of the gate GN4, and the output terminal Q3 of the flip-flop FF3 is applied to the other input terminals of the NAND gates G1 and G2 and the NOR gate GN4, and thus the NAND gates G1 and G2. And the output terminal signals of the NOR gate GN4 are the same as those of (HJ) in FIG.

That is, the output terminal of the NAND gate G2 becomes 'low' only when both input signals are 'high' and is applied as a clock signal of the flip-flop (FF11-FF12), and when both input signals are 'high', The output terminal signal of the NAND gate G1, which is converted to 'low', is applied to one input terminal of the NAND gates G7 and G10, converting its output terminal to 'high', and at the same time through the inverter NR3. As in (K), it is inverted to a 'high' state and is applied to the reset terminal R of the flip-flop (FF6-FF10), so that the count value of the 31-counter counter (3) is reset to '0', (GN4) is converted to 'high' only when both signals are input to the two input terminals and is applied to one input terminal of the NAND gate G15.

In addition, only when the output of the NAND gate G6 and the output Q11 of the flip-flop FFl1 are the same (that is, when all are 'low' or 'high'), the NOR gate GN7 and the NAND gate G11 And the NAND gate G13 only when the output of the NAND gate G12 passing through the inverter NR6 becomes 'high' and the output of the NAND gate G9 and the output terminal Q12 signal of the flip-flop FF12 are the same. ), The output of the NAND gate Gl4 becomes 'high' through the NOR gate GN8 and the inverter NR7. If the output of the NOR gate GN4 is 'high', the output of the NAND gate G15 is obtained. Becomes " low " and is applied as the clock signals of the deflip-flops FF13 and FF14.

On the other hand, the output signal CFG of the basic clock as shown in FIG. 3A and the capstan frequency oscillator as shown in FIG. 3L is the clock terminal CK and the input terminal D of the flip-flop FF4. When applied to, respectively, its output terminal ) Outputs signals such as (M) and (N) in FIG. 3, with outputs Q4 and Q4 of the single high flip-flop (FF4) whose capstan frequency is 'high'. When the signal is input in the 'low' state, it is output in the 'low' and 'high' states, respectively, and is applied to the input terminal D of the flip-flop FF5 and one input terminal of the NOR gates GN1 and GN2.

Therefore, the outputs Q5 and Q5 of the flip-flop FF5 operating at the falling edge of the basic clock frequency are delayed for one period of the basic clock frequency as shown in (O) and (P) of FIG. 3, respectively. You will see this output The signal is applied to the other input terminal of the NOR gates GN1 and GN2, respectively.

Accordingly, the output of the deflip flop (FF4, FF5) When all of them are 'low', the output of the NOR gate GNl is 'high' as shown in Fig. 3 (Q), so that the rise time of the capstan frequency can be detected, and the output of the deflip-flops FF4 and FF5. When both of them are 'low', the output of the NOR gate GN2 is 'high' as shown in (R) of FIG. 3 so that the fall time of the capstan frequency can be detected.

In addition, when both outputs are 'low', the output of the NOR gate GN3 becomes 'high' as shown in FIG. 3 (S), which is a result of multiplying the capstan frequency by two times.

On the other hand, since the output signal of the NOR gate GN3 as shown in (S) of FIG. 3 is applied to one input terminal of the NAND gates G4 and G5, the coefficient value output through the NOR gate GN6 and the inverter NR5. Can be applied to one input terminal of the NAND gates G6 and G9 via the NAND gates G4 and G5, and at the same time, the inverter is inverted as shown in FIG. The output signal of the gate GN6 is applied to the clock signal of the flip-flop FF6 through the NOR gate GN5.

Therefore, the reset state of the de-flip flop FF6-FF10 is determined by the output state of the inverter NR3, and the counting is started by the output signal of the north gate GN5.

Also, when the count value is '20' (ie, Q8 = 'high', Q10 = 'high'), the output of the NAND gate G8 becomes 'low', and the count value is '11' (ie, Q6, Q7, Q9 = 'high' NAND gate (G3) output is 'low', NAND gate (G3, G8) outputs all 'low' (ie, count value '31') NOR The output of the gate GN6 becomes 'high'.

Therefore, the 'high' signal is applied to one input terminal of the NAND gate G4. At this time, the 'high' output of the NOR gate GN6 causes the output of the NAND gate GN5 to always be 'low', so that the counter 3 is The count value stops at '31'.

For example, assuming that the control pulse frequency is 30Hz and the low speed (SP) mode is 2 hours mode, and the capstan frequency is 720Hz, its doubled frequency is 1440Hz, and the standard speed (LP) mode is 4 hours mode. The capstan frequency is 360 Hz, and the doubled frequency is 720 Hz. When the high speed mode (EP) is in the 6 hour mode, the capstan frequency is 240 Hz, and the double frequency is 480 Hz.

Therefore, the low speed capstan frequency (SP CFG) in one cycle of the control pulse at 30 Hz at low speed (SP) is 1440/30 = 48 cycles, and the capstan frequency (LP CFG) at standard speed (LP) is 720/30 = 24. The high speed capstan frequency EP CFG at high speed EP is 480/30 = 16.

In this case, if the boundary between EP and LP is '20', if the capstan frequency (CFG) of '20' or less is present, EP, if the capstan frequency (CFG) between '21' and '31' is present, LP, '31' 'If the above capstan frequency exists, it is determined by SP.

In addition, such determination is determined for each period of the control pulse, and the output of the NOR gate GN4 is not transmitted to the clock terminal CK of the flip-flops FF13 and FF14 unless they are the same as the determination data of the previous state. As a result, the outputs Q13 and Q14 are not changed, and the previous state is maintained as it is. This means that every cycle discrimination data is the same as the discrimination data of the previous state.

Each cycle, the discrimination data is output through the NAND gates G6 and G9 and output through the flip-flops FFll, FF13 and FFl2 and FF14, respectively.

That is, in LP mode, the NAND gates G6 and G9 and the outputs of the flip-flops FF11-FF14 are all low, and in the LP mode, the NAND gates G6 and the flip-flop FF11. , FFl3) are all 'high', NAND gate (G9) and dip-flop (FF12, FF14) outputs are all 'low', NAND gate (G6, G9) and deflip when in SP mode As the outputs of the flops FF11 and FF14 are all high, the output of the inverter NR8 is high when in EP mode, and the output of NOR gate GN9 is high when in LP mode. '. In the SP mode, the 'low' output of the NAND gate G16 is inverted to 'high' through the inverter NR9 and output.

As described above, according to the present invention, even if the control pulse reproduced from the tape or the capstan frequency detected by the capstan motor is unstable, each of the high speed, standard speed, low speed, and operation modes (EP, LP, SP) can be accurately determined. Of course, it is possible to determine the accuracy of the discrimination by using the multiplication of the capstan frequency, and it is possible to perform a more stable discrimination function by discriminating the previous cycle discrimination data and the current cycle mode of the control pulse.

Claims (5)

Receiving the control pulse (CTL) and the clock pulse reproduced from the video tape, the counter 3 resets the counter 3 at each period of the control pulse and generates a clock signal for transmitting the mode (SP, LP, EP) discrimination data. And a multiplication unit for multiplying and outputting the output signal CFG of the capstan frequency generator for phase / speed detection of the capstan motor during a constant speed drive of the video tape by a predetermined multiple suitable for counting and decoding. 2) and a counter 3 which counts the multiplied CFG signal output from the multiplication unit 2 and supplies the count result to the discrimination data transmission unit 4 when the count value becomes a reference value set for mode discrimination. And discrimination data for decoding the output value of the counter 3, determining the mode discrimination data as a result, and outputting a mode discrimination signal corresponding to a predetermined reproduction speed (high speed, standard speed, and low speed). A playback tape speed automatic discrimination circuit in a VCR composed of a sending unit (4). The clock generator (1) according to claim 1, wherein the reset and discrimination data transmission clock generator (1) includes a plurality of flip-flops (FF1, FF2, FF3) for delaying the control pulse (CTL) in clock units and the output of the flip-flop. And a NAND gate (G1) for outputting a reset signal every one period of the control pulse by a logical combination of. A playback tape speed automatic discrimination circuit in a VCR comprising a NOR gate (GN4), a NAND gate (G2), and an inverter (NR2) for supplying a clock by logically combining the outputs of the flip-flop. 2. The flip-flop (FF4, FF5) according to claim 1, wherein the multiplication part (2) is for latching a CFG signal. And a plurality of NOR gates (GN1, GN2, GN3) for outputting a CFG signal multiplied by two by logically combining the output of the flip-flop. 2. The counter (3) according to claim 1, wherein the counter (3) includes flip-flops (FF6, FF10) for counting the input CFG signal, a knock gate (GN5) and an inverter (NR4) for clock and reset input of the flip-flop. (NR3), NAND gates G3 and NOR gates GN6 for outputting the LP / SP classification pulses from the count output, and NAND gates G6 for outputting the pulses with EP / LP classification from the count output. ) And an inverter NR5, and a playback tape in a VCR composed of outputs of the gates NR5 and GN6 and NAND gates G4 and G5 for outputting a final count value for mode discrimination according to the multiplied CFG signal. Speed automatic discrimination circuit. 2. The NAND gate (G6, G7, G9, G10) for inputting the counter count output as mode discrimination data, and the flip-flop (FF11) for latching the input data according to claim 1, , FF12, flip-flops FF13 and FF14 for latching and outputting data of the flip-flops FF11 and FF12, and NAND gates G11-G15 and inverters NR6 for inputting a clock to the flip-flop. , NR7) and NOR gates GN7 and GN8, an inverter NR8 that inverts the outputs of the flip-flops FF13 and FF14 and outputs them as EP mode discrimination data, and a NOR gate GN9 that outputs LP mode discrimination data. )Wow. Automatic playback tape speed discrimination circuit in VCR composed of NAND gate (G16) and inverter (NR9) output as SP mode discrimination data