KR950009433B1 - The distributed queue dual bus communication system - Google Patents

Abstract

The system comprises a FIFO queue for storing an OA segment; a DQSM state machine for maintaining a count down state so as to transfer the segment when the FIFO queue has at least one segment, and outputting the segment when a busy slot bit is "0"; a ROM state machine for receiving request information when the DQSM state machine receives the QA segment from the FIFO queue, sending the request information to a reverse bus B of the DQSM state machine when the request bit is "0", performing a request bit transmission control function when own request is desired to be sent, and outputting a relative information; a LMSM state machine for receiving the information from the DQSM state machine and the FIFO queue, and measuring a time average value of the traffic load for the own node and a bottom node; a SESM state machine for receiving the information on the presence/absence of the performance of the segment from the LMSM state machine and the request bit information from the RQM and RCSM state machines; and a RCSM state machine for receiving a request cancellation information from the DQSM state machine and the SESM state machine, and informing the SESM state machine of the result.

Description

Injection queue dual bus communication system with adaptive erase node function

1 is a structural diagram of a distributed queue dual bus communication system.

2 is a frame and slot configuration diagram.

3 is an operation diagram of an RQ counter in an idle node.

4 is an operation diagram of an RQ and CD counter at a node in a countdown state.

5 is a diagram illustrating the interaction between FIFO queue, DQSM and RQM state machines.

6 is a diagram for explaining segment transmission operation.

7 is a diagram illustrating a segment transmission operation in a distributed queue double bus communication network having a destination release (DR) function.

8 is a diagram illustrating a segment transmission operation in a distributed queue dual bus communication network having an erase node (EN) function.

9 is a block diagram of an adaptive erasing node (AEN) of the present invention.

Figure 10 is a block diagram of the SESM state machine configuration.

11 is a block diagram of an RCSM state machine configuration.

12 is a block diagram of an LMSM state machine configuration.

13 is a block diagram of a DQSM state machine configuration.

14 is a block diagram of an RQM state machine configuration.

* Explanation of symbols for main parts of the drawings

4: FIFO queue 5: DQSM state machine

6: RQM state machine 8: SESM state machine

9: RCSM State Machine 10: LMSM State Machine

The present invention provides a distributed queue double bus (DQDB) having an adaptive erasure node (AEN) function used to perform multimedia transmission services such as data, voice, and video at a high transmission rate of 150 Mbps. Dual Bus) communication system.

Distributed queue dual bus communication system is a communication system that imagined and standardized high-speed local network by American Association of Electrical and Electronic Engineers, and is used to provide high-speed multimedia transmission service.

However, in the distributed queue dual bus communication system, each node in the network has a problem in that access opportunities are unfair depending on the position of the node when the bus is accessed. This unfairness is even worse when the traffic load on the network is high.

In distributed queue dual bus communication, segment erasing is a function that allows slots to be reused after they pass through their destinations. Therefore, the efficiency of the entire network can be increased, thereby improving the fairness of access for each node in the network. There are two types of segment erasing methods for playing slots. One is a destination release (hereinafter referred to as DR) in which all nodes in the network have a segment erasing function, and the other is within a network. Erasing node (hereinafter referred to as EN) method in which a specific node is responsible for segment erasing.

The former method has good throughput, but delay time is caused by buffering the destination address at each node, and the throughput at the upstream node is increased as the number of requests from the lower node is increased under high traffic load. Is lowered. The latter scheme is smaller and simpler to implement in the network than the former, but it is inefficient when the position and number of nodes in the network have a direct effect on the throughput and the traffic load distribution of the network is unbalanced.

Therefore, the present invention devised to solve the problems of the prior art is adapted to act as a base node in a low traffic load state and to operate as an erase node only in a high traffic load state, that is, adapting to the size of the traffic load change in the network. The purpose of the present invention is to provide a distributed queue double bus communication system having an adaptive erasing node (AEN) function, which has good performance and excellent throughput, delay time, and fairness in an overloaded state.

In order to achieve the above object, the present invention provides a distributed queue double bus (DQDB) communication system having two unidirectional buses and a plurality of nodes connected along the unidirectional bus, each node transmitting itself to a destination node. A FIFO queue that stores a QA segment created for the purpose, and is connected to the FIFO queue and is counted for transmission of a segment that enters via bus A when it is normally idle and has at least one segment in the FIFO queue. The DQSM state machine outputs a segment when an empty slot (when the busy bit is '0') is passed to bus A and the QA segment is connected to the FIFO queue to transfer a QA segment from the FIFO queue to the DQSM state. At the same time as the machine receives the request, it receives request information and an empty slot (request bit is '0') on bus B, the reverse bus of the DQSM state machine. When a request is made to send a request to each node, the request is controlled to send a request each time the user passes. RQM state machine that performs bit transmission control function and outputs relevant information, and is connected to receive information from DQSM state machine and FIFO queue to measure the temporal average value of traffic load on its own node and lower node in network. Provides a LMSM state machine for outputting a result, information on whether or not a play slot is generated by the RQM state machine, and whether or not to perform a segment erase function from the LMSM state machine and also requests from an RQM state machine. Receives bit information and segment of each slot passing through the forward bus when performing segment erase function. And a SESM state machine which performs a function of clearing the previously arrived and buffered segment and notifying the result to the RQM state machine if the bit is buffered and the bit is set to '1' according to the frame PSR bit. Segment erasing information is input from the SESM state machine and request cancellation information is received from the DQSM state machine and the SESM state machine, and the request arriving from the lower node side is canceled through the reverse bus. A distributed queued dual bus communication system comprising the node as an adaptive erasing node having an RCSM state machine notifying a SESM state machine.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a structural diagram of a distributed queue double bus (DQDB) communication system, in which two unidirectional buses (bus A and bus B) and head nodes 1a or 1n are connected along the unidirectional buses (bus A and bus B). And a plurality of nodes 1, logically having a bus structure, but physically in the form of a ring. Each bus has a head node (1a for bus A, 1n for bus B) and an end node (1n for bus A and 1a for bus B).

Both buses A and B allow bidirectional communication between any two nodes in the network. Therefore, the node 1 to communicate with must know which bus to use to communicate with the counterpart node 1. If both buses are used for communication at the same time, the communication capacity of the network is twice that of using a single bus.

The operation of both buses is independent in transferring data, and data on each bus is loaded into a slot of fixed length, which is generated by the head node 1a or 1n of each bus. That is, node 1 writes data to a slot by a bus access procedure, and this flow ends at end node 1n or 1a. Here, the bus A used for transmitting data is called a forward bus, and the bus B used for requesting a transfer request is called a reverse bus.

2 is a frame and slot configuration diagram of a distributed queue dual bus communication system. A frame includes a plurality of slots, a frame header, and a spare area. The QA is used to provide non-isochronous services. The fixed information length of a (Queued-Arbitrated) slot is called a QA segment. Each slot has a size of 53 octets and consists of an access control field (hereinafter referred to as an ACF) and one segment that forms slot information, where the segment consists of a segment header and a segment payload. .

Within the slot's ACF, there are control bits such as busy bits and request bits. In this case, the busy bit indicates whether a slot is used, and the request bit indicates that there is data waiting in the queue for transmission, and three bits are used as three priorities are provided.

The PSR (Previous Segment Received) bit is used for slot reuse. When set to "1" in a slot, it means that the segment of the previously arrived slot is copied and passed from the upper node on the same bus. In this case, the previously arrived slot can be reused. The slot type bit indicates whether the data carried in the slot is a QA segment, and the reserved area is a reserved bit designated for future use. Each node 1 operates a counter for each bus, and uses them to determine when data queued in its own node can transmit.

3 is an operation diagram of a request (request (hereinafter referred to as RQ) counter) 2 at an idle node of a distributed queue dual bus communication system, where an idle node has no data to transmit. Refers to a node.

When a node (1) has data to transmit to the forward bus, it makes the request bit of the slot passing through the bidirectional bus '1', and when the slot passes through an idle node, its RQ The value of the counter 2 is increased by one. When an empty slot passes through the forward bus, the value of the RQ counter 2 is decreased by one, which is an operation that is expected in advance to expect that the empty slot will be used by some downstream node in a short time. By managing the value of the RQ counter 2 in this way, each node 1 can know how many segments are currently waiting at its lower node by reading the current value of the RQ counter.

4 is an operation explanatory diagram of an RQ counter 2 and a countdown counter (hereinafter referred to as CD) 3 in a node in a countdown state of a distributed queue dual bus communication system. Refers to a node having a QA segment to transmit.

That is, in the node where the QA segment to be transmitted is generated, the current value of the RQ counter 2 is moved to the CD counter 3, the RQ counter 2 is cleared to '0', and the countdown state is entered. At this time, the value of the CD counter 3 of the node is a value indicating how many times the QA segment to be transmitted is generated in time among the QA segments waiting in the queue of the lower node including the node. The node entering the countdown state increments the value of the RQ counter 2 by one when the request bit passes through the reverse bus. When an empty slot passes by the forward bus, the value of the CD counter 3 is decreased by one, until the segment is transmitted to the next empty slot of the forward bus until the value of the CD counter 3 becomes '0'. It becomes possible. Here, the value of the CD counter 3 is '0' means that the segment is no longer present in the standby because it is generated before the segment to be transmitted by the lower node.

As can be seen from the description of FIG. 3 and FIG. 4, in order to transmit a QA segment in a node, it is necessary to wait until there is no QA segment created and waiting before the segment to be transmitted in its own node. In addition, even if the request bit is not written on the reverse bus, access is possible if the value of the CD counter 3 is '0' because the operation of writing the request bit and the transmitting of the QA segment are independent. In this way, in accessing the forward bus, the network of a distributed queued dual bus communication system constitutes a first-in first-out (FIFO) queue, so slots are wasted in the network if there are always segments to transmit. It doesn't work.

On the other hand, the RQ counter and CD counter described in FIGS. 3 and 4 are logical components of the DQSM state machine 5 which will be described later in FIG.

5 is a diagram illustrating an operation relationship between a FIFO queue 4 and a Distributed Queue State Machine (DQSM) state machine (5) and a REQ Queue Machine (RQM) state machine (6) in a distributed queue dual bus communication system. The state machines configured to process distributed queues within 1) show the interoperation relationship until the QA segment is created and transmitted.

The FIFO queue 4 is where each node 1 waits for a created QA segment for transmission to a destination node, and a plurality of segments may be stacked.

When the DQSM state machine 5 which performs the functions of the RQ counter and CD counter described in FIGS. 3 and 4 is in an idle state and has at least one segment in the FIFO queue 4 of bus A, , Only one segment comes in. At this time, the DQSM state machine 5 changes to the countdown state for transmission of the incoming segment, the RQ counter 2 value is transferred to the CD counter 3, and then the RQ count 2 value is cleared. The segment is then sent out when the value of the CD counter (3) is '0' and an empty slot (busy bit is '0') on bus A passes.

The RQM state machine 6 operates independently of the DQSM state machine 5, and receives request information at the same time as the DQSM state machine 5 receives the QA segment from the FIFO queue 4, and then receives the DQSM state machine. A request is sent to bus B, which is the reverse bus of (5). Whenever an empty slot (when the request bit is '0') passes on bus B, a request is issued, where the REQ (REQuest) in the RQM state machine (6) indicating the number of request occurrences. The counter value is decremented by one.

FIG. 6 is an explanatory diagram of a segment transmission operation in a distributed queue dual bus communication network in which a slot having a destination address (DA) of a node 4 passes a bus in the network.

Slots passing through the destination sent from the upper roadside are kept in the network until discarded at the end node 1n, so that each node 1b-1f in the network is not able to use the slot, and thus the bus utilization rate in the network is low.

On the other hand, in the distributed queue dual bus communication method, since a message is transmitted in units of segments in a slot having a predetermined length, the segment arriving at the destination node 1b may be erased and reused at the lower node side 1c-1f. The segment erasing function is used to reuse the transmitted slot to the destination node 1b. In this case, the lower nodes 1c-1f may be given more transmission opportunities to lower transmission delay and increase efficiency of use.

In particular, it is possible to improve the fairness of the transmission opportunity to each node 1 by increasing the bus utilization rate in the network. There are two types of segment erasing functions, DR and EN.

7 is a diagram illustrating a segment transmission operation in a distributed queue dual bus communication system network having a destination release (DR) function.

The destination address of the slot arriving at its node is examined and the segment is erased when it is identical to its own address, and all nodes 1 have a segment erase function. That is, when the destination node addresses are 4, 6, and 8, the slots may be presented at node 4 (1b), node 6 (1d), and node 8 (1f), respectively.

Therefore, the bus utilization rate can be increased because the number of times is used in the network until it is generated from the head node 1a of one slot and dissipated at the end node 1n. However, all nodes 1 must buffer the segment until the destination address of the passing slot is determined and the transmission delay in the network is increased due to the time required to decode the destination address.

8 is an explanatory diagram of a segment transmission operation in a distributed queue dual bus communication system network having an erase node (EN) function, in which a specific node 1c is configured to have a segment erase function at a specific position in the network. The node 1c of is called EN (1c). EN 1c checks the PSR bit in the slot and erases the segment of the previously arrived slot when the PSR bit is set to '1'. This method requires only one slot length segment buffering within EN (1c), and uses only PSR bits to perform the segment erase function. In the EN scheme, slots passing through the destination cannot be played back before passing through EN 1c. That is, when the destination node address is 4, the slot is played only in the erasing node (EN) 5 (1C) having the segment erasing function, and the reproduced slot is reused by the lower node 1d-1f from the EN (1c). can do.

According to these operating characteristics, the EN method requires the determination of the optimal EN position and the number of ENs to obtain the maximum efficiency in the network whenever the network configuration is changed, and when the traffic load occurs intensively at a specific position in the network. Alternatively, when the traffic load changes dynamically, the effect of the application of EN (1c) is reduced.

In the DR method and the EN method as described above, request bits are increased as much as the number of request bits used by the lower node is increased by the slot erased by segment erasing, so that the number of request bits that arrive at the upper node is increased. As the number of times of use of slots decreases, the access delay increases, and conversely, inferiority of the lower nodes increases the use of empty slots, resulting in unfairness of access delay.

In other words, the closer to the end node 1n, the greater the waste of bandwidth, and the closer to the head node 1a position, the greater the access delay time and the lower the throughput. Therefore, in order to effectively use the increased bandwidth in the network, it is necessary to cancel the number of requests in the fastest time as the number of the used slots is used in the lower node.

The present invention is an adaptive cancellation node (AEN) method devised to solve the above problems, all nodes in the network can operate as an EN having a segment erasing function, and dynamically As a result, the EN position is changed and the request is canceled in the shortest time due to the use of the playback slot to maximize the efficiency of the segment erase function. That is, each node cancels a request for each slot that is reproduced when operating as EN so that the segment erase function can be operated in the same manner as the basic node. To this end, segmented erase, request cancellation, and traffic load measurement functions have been added to the basic distributed queue dual bus communication function.

Then, these added functions are performed at the front end of the DQSM state machine 5 and the RQM state machine 6 so that the node can use the newly reproduced slot.

9 is a block diagram of an adaptive erasing node 7 according to the present invention, in which a segment erasing function is performed in addition to the DQSM state machine 5 and the RQM state machine 6 of the basic node. State Machine (8) by adding a state machine (8), Request Cancellation State Machine (RCSM) state machine (9) performing a request cancellation function, Load Monitoring State Machine (LMSM) state machine (10) for measuring the traffic load in the network Configure.

Here, the LMSM state machine 10 receives the information from the DQSM state machine 5 and the FIFO queue 4 and measures the temporal average value of the traffic loads for its own node and the lower nodes in the network, and then measures the SESM state machine ( 8) It informs the result.

The SESM state machine 8 receives information on whether or not to perform the segment erase function from the LMSM state machine 1, and also receives request bit information from the RQM state machine 6 and the RCSM state machine 9, and sends the segment report. When performing a function, buffer the segment of each slot passing through the forward bus, and if the PSR bit is set to '1' according to the PSR bit, erase the previously arrived and buffered segment and return the result to the RCSM state machine (9). ) And the RQM state machine (6).

The RCSM state machine 9 receives request cancellation information from the DQSM state machine 5 and the SESM state machine 8, and cancels a request arriving from a lower node side through the reverse bus. The function notifies the SESM state machine 8 of the result.

The DQSM state machine 5 is the same as the operation of the basic distributed queue dual bus communication method, and performs a function of informing the LMSM state machine 10 and the RCSM state machine 9 related information about the operation state in the network.

In addition to the basic distributed queue dual bus communication operation, the RQM state machine 6 receives information related to whether a play slot is generated from the SESM state machine 8 and generates a play slot at its own node. When the request is to be sent, the request bit transmission control function is performed, and the related information is sent to the SESM state machine 8.

The FIFO queue 4 stores segments to be transmitted by the node 1 and transmits the related information to the DQSM state machine 5, the RQM state machine 6, and the LMSM state machine 10.

FIG. 10 is a block diagram showing the configuration of the SESM state machine 8 of the adaptive erasing node according to the present invention, and receives the traffic state information in the network from the LMSM state machine 13 to determine whether to perform the segment erasing function. A segment erasing function determination block 13 for controlling a block, buffering a segment in a slot arriving from an upper node of the bus A when performing the segment erasing function, and performing a segment erasing function under the control of the RSR bit check block 12. Segment buffer block 11, PSR bit check block 12, RCSM state machine for checking whether the PSR bit is set for the slot information arriving when performing the segment erase function and transmitting the result to the request bit control block 14 (9) and the request bit control function from the RQM state machine (6) and the result is determined whether the segment erase function execution block 13 and the RCSM state machine (9) and It consists of a request bit control block 14 which delivers to the RQM state machine 6.

11 is a block diagram of the RCSM state machine 9 of the adaptive erasing node according to the present invention, and receives information from the SESM state machine 8 and the slot time measurement block 16 to determine whether to cancel the request. Intranet operation state from the request bit cancel decision block 15, the DQSM state machine 5, which delivers the result to the request bit cancel block 17 and the SESM state machine 8. Receives the relevant information from the slot time measurement block 16 and the request cancellation determination block 15, which perform the function of receiving the information and measuring the slot time and sending the request to the request bit cancellation determination block 15. And a request bit cancel block 17 which performs a function of canceling a corresponding request bit passing through the reverse bus.

12 is a block diagram of an LMSM state machine 10 configuration of an adaptive erasing node according to the present invention, which receives in-network operating state related information from a DQSM state machine 5 and a FIFO queue 4 to measure traffic load in a network. The traffic load measurement block 18 and the traffic load measurement block 18 constitute a traffic load state determination block 19 which determines whether or not the traffic load is greater than or equal to the reference value and delivers it to the SESM state machine 8.

FIG. 13 is a block diagram showing the configuration of the DQSM state machine 5 of the adaptive erasing node according to the present invention. FIG. 13 shows the segment related information in the slot passing through the forward bus and the reverse bus, and the result is the segment queue block 21 and the LMSM state machine. (10) and the related information from the in-network operating state measurement and monitoring block 20, the in-network operating state measurement and monitoring block 20, and the FIFO queue 4, which perform a function of transferring to the RCSM state machine 9; And a segment queue block 21 which performs a function of transmitting a segment queue waiting to be transmitted to the forward bus.

14 is a block diagram of the RQM state machine 6 of the adaptive erasing node according to the present invention. A generation check block 22, a FIFO queue 4 and a playback slot generation check block 22, and a request bit cancel block that perform a function of transmitting the request bit to the request bit transmission control block 23; Request bit transmission control block 23, FIFO queue 4, and request bit transmission control block 23, which receive the relevant information from (24) and control the transmission of request bits. It consists of a request bit queue block 24 that receives the information and transmits the request bit that is waiting to be transmitted to the reverse bus and transmits the result to the request bit transmission control block 23. do.

On the other hand, the DQSM state machine, RQM state machine, SESM state machine, RCSM state machine and LMSM state machine is composed of a memory element, a buffer element, a counter and various logic to perform the storage processing and transmission function of the message.

The operation characteristics and the improvement effect of the distributed queue dual bus communication method having the AEN method with the structural characteristics as described above can be known by analyzing the result of comparing the fairness of the access delay time and access delay time according to the traffic load variation. have.

Here, the DQDB network used for the operation characteristic analysis is configured such that the total number of nodes is equally spaced by each node, and the compared schemes are the basic distributed queue double bus communication scheme (hereinafter referred to as DQDB-). basic method), DR method EN method (when two erasing nodes are used in node numbers 6 and 12), and AEN method. Each node generates packets according to Poesson distribution, one packet is divided into 5 segments on average according to the geometric distribution, and the generated packets have the destination node address in uniform distribution. to be. In particular, the message distribution at each node is assumed to be the same, and a method of varying the traffic load by changing the message generation rate is used.

On the other hand, as an evaluation factor used for the operation characteristics, the average access delay time is a network wait time in the FIFO queue from when the packet is generated in the node to the segment and starts waiting in the FIFO queue until it is transmitted to the bus. The smaller the average value of each node in the network, the better. The fairness of the access latency is the ratio between the maximum value and the minimum value of the average access delay time of each node in the network.

[Table 1] below is a comparison table of average access delay time for each traffic load.

TABLE 1

As shown in [Table 1], in all methods, the access delay time is proportional to the traffic load increase. In terms of the size and the increase rate of the access delay time, the AEN method is relatively smaller than other methods, and the traffic load is increased. As a result, the improvement effect is even greater.

When the traffic load is 100%, it is improved by about 11 times compared to the basic distributed queue dual bus communication method, and about 1.2-2.1 times compared to other methods.When the traffic load is 140%, about 19.1 times and about 2.3, respectively. -8.3 times better

[Table 2] below is a fairness comparison table of average access delay time by traffic load.

TABLE 2

The fairness of the AEN method is superior to other methods as the traffic load increases. The basic distributed queue dual bus communication method has been shown to be relatively good, but in this case, the overall characteristics are poor because the access delay time is much higher than that of other methods.

Except for the AEN method and the basic distributed queue dual bus communication method, the fairness worsens in the order of the EN method and the DR method as the traffic load increases.

According to the above results, the distributed queue dual bus communication system having the AEN method of the present invention is very small in terms of overall access delay time even when the traffic load is increased, and excellent in fairness according to the efficient distribution of the increased bandwidth. In particular, the efficient use of bandwidth in the network increases the bus utilization rate, and thus the throughput is improved, and the access delay time is hardly affected even when the network transmission speed or transmission distance is changed. There is a possible advantage, and it can be usefully applied to subscriber network matching communication system in B-ISDN (Broad-Intergrated Service Digital Network).

Claims (6)

In a distributed queue double bus (DQDB) communication system having two unidirectional buses (bus A, bus B) and a plurality of nodes 1a or 1n connected along the unidirectional buses (bus A, bus B), A FIFO queue (4) that stores the QA segments created for each node to transmit to its destination node, and is connected to the FIFO (4) queue and is normally idle and at least one or more in the FIFO (4) queue. DQSM state machine that waits in the countdown state for transmission of a segment coming on bus A when it has a segment and outputs the segment when an empty slot (busy bit is '0') passes on bus A ( 5) and the reverse bus of the DQSM state machine 5 by receiving request information at the same time as the DQSM state machine 5 receives the QA segment from the FIFO queue 4 connected to the FIFO queue 4. In slot B, an empty slot (request est) Controls to send a request whenever the bit is '0'), and receives a play slot creation information and generates a play slot in its own node. The RQM state machine 6 which performs a request bit transmission control function and outputs relevant information when receiving a message, and receives the information from the DQSM state machine 5 and the FIFO queue 4 is connected to the network. An LMSM state machine 10 which measures a temporal average value of traffic loads of its own node and a lower node in the node and outputs a result, and information on whether to perform a segment erase function from the LMSM state machine 10 and also It receives request bit information from the RQM state machine (6) and the RCSM state machine (9), and buffers the segment of each slot passing through the forward bus when performing the segment erase function. If the bit is set to '1' according to the multi-frame PSR bit, the SESM state machine 8 performs a function of erasing the previously arrived and buffered segment and informing the result to the RQM state machine 6; Receive request request information from the DQSM state machine (5) and the SESM state machine (8), cancel the request arriving from the lower node side through the reverse bus, and return the result to the SESM state machine (8). A distributed queued dual bus communication system, comprising the nodes (1a to 1n) as an adaptive erasing node (7) having an RCSM state machine (9) to notify. 2. The segment according to claim 1, wherein the SESM state machine 8 receives the in-network traffic state information from the LMSM state machine 13 to determine whether to perform a segment erase function, and controls the segment erase function according to the result. Erasing function determining means (13), segment buffer means (11) for buffering a segment in a slot arriving from an upper node of bus A when performing a segment erasing function and performing a segment erasing function according to an input control signal; PSR bit checking means 12 for controlling the segment buffer means 11 and checking whether or not the PSR bit in the frame is set for the slot information arriving when performing the segment erasing function and outputting the result, and the RCSM state machine 9 Request from the RQM state machine 6 and request information related to the request and the PSR bit check information from the PSR bit check means 12. Distributed queue comprising a segment erase function determining means (13) and a request bit control means (14) for transmitting the result to the RCSM state machine (9) and the RQM state machine (6). Heavy Bus (DQDB) Communication System. 2. The RCSM state machine (9) according to claim 1, wherein the RCSM state machine (9) receives in-network operation state information from the DQSM state machine (5) and measures slot time to measure slot time (16) and the SESM state machine (8). Receiving request information from the slot time measuring means 16 and determining whether to cancel the request and outputting the result to the SESM state machine 8; A request bit canceling means (17) which performs a function of canceling a corresponding request bit passing through the reverse bus B by receiving the request decision result information from the request canceling determining means (15); Distributed queued bus (DQDB) communication system, characterized in that. According to claim 1, The LMSM state machine 10, Traffic load measuring means for measuring the traffic load in the network by receiving the operation information related to the network in the network from the DQSM Sant'Amer (5) and the FIFO queue ( 18) and traffic load state determining means 19 which receives the traffic load information from the traffic load measuring means 18 and determines whether or not the traffic load is equal to or higher than a reference value and delivers it to the SESM state machine 8. Distributed queued bus (DQDB) communication system characterized in that it comprises. 2. The DQSM state machine (5) according to claim 1, wherein the DQSM state machine (5) monitors various segments related information in the slots passing through the forward bus A and the reverse bus B, and the result is the LMSM state machine 10 and the RCSM state machine 9. Intra-network operation state measurement and monitoring means 20 for outputting through the network operation state measurement and monitoring means 20 and the FIFO queue (4) to receive the department-related information to the segment queue waiting to be transmitted to the forward bus Distributed queue double bus (DQDB) communication system, characterized in that it comprises a segment queue means (21) for performing the function of transmitting. The reproducing apparatus according to claim 1, wherein the RQM state machine (6) receives the play slot related information from the SESM state machine (8), checks whether a play slot is generated, and outputs the result back to the SESM state machine (8). Request bit transmission control means 23 for receiving the relevant information from the slot generation confirmation means 22, the FIFO queue 4 and the playback slot confirmation means 22, and controlling the transmission of the request bits, and the FIFO. Receives the relevant information from the queue 4 and the request bit transmission control means 23, transmits the request bit waiting to be transmitted to the reverse bus, and sends the result to the request bit transmission control means 23. A distributed queue double bus (DQDB) communication system comprising a request bit queuing means for performing a function of delivering.