KR950009071B1 - Data transmission control device of hipi-bus - Google Patents

Abstract

The device reads/writes data in the memory through HiPi bus and improves the bus efficiency of usage time. The device includes a microprocessor(9), a HiPi bus(20), a data transfer controller(11) which generates control signals, an address arbiter(12) which executes address arbitration by control signal, an address buffer(13) which drives the address bus at the specified time of bus cycle, a data buffer(14) which drives the data bus at the specifeid time of write timing, an address response latch(15) which decides the address, a data response latch(16) which decides the data, a comparator(17) which compares the transfer number with the data receiving number, a data latch(18) and a parity checker(19).

Description

HiPi Bus Data Transfer Control

1 is a schematic system configuration diagram of a conventional shared bus multiprocessor.

2 and 3 are exemplary timing diagrams of read bus cycles and write bus cycles on a bus.

4 is a block diagram of a data transmission control apparatus according to the present invention.

5 is a block diagram of the data transfer controller shown in FIG.

6 is a data transmission control flowchart of the data transmitter 11;

7 is an address arbitration control flowchart of the address arbiter 12. FIG.

8 and 9 illustrate timing diagrams of a read bus cycle and a write bus cycle of FIG. 4.

* Explanation of symbols for main parts of the drawings

9 processor 11 data transfer controller

12: address arbiter 13: address buffer

14: data buffer 15: address response latch

16: data response latch 17: comparator

18: data latch 19: parity checker

111: Arbitration Requester 112: Address Buffer Controller

113: data controller 114: cycle terminator

The present invention relates to a data transfer apparatus for performing data read or write access to a memory through a HiPi bus used as a data transfer bus of a unique memory multiprocessor.

In general, efficient use of the bus is a major factor in improving system performance, because processors must send and receive addresses and data over the bus to access memory.

Due to the above-described causes, many schemes have been proposed for the purpose of efficient use of buses, and a representative scheme is a hi-fi scheme.

The data transmission method of the hi-fi bus is a method in which one bus cycle is generated by a processor so that a plurality of processors can use a bus, and permission of the bus is granted to other processors during a memory access time. .

The above-described scheme will be briefly described with reference to the accompanying drawings.

FIG. 1 is a schematic system configuration diagram of a conventional shared bus multiprocessor. FIG. 2 and FIG. 3 are exemplary timing diagrams of a read bus cycle and a write bus cycle on a bus.

Each operation of the bus cycle as described above operates based on the bus clock and uses one clock.

The processor gaining permission in the address arbitration (see also second (b)) drives the address and control signals to the address bus (see also second (c)), as shown in the second (d) diagram. Receive an address response from memory.

The processor then waits for data to arrive in memory (see also second (e)).

As described above, referring to the data write operation according to the data read operation, the operations up to address arbitration (see also third (b)) and driving of the address bus (see also third (c)) in response to the bus cycle are described above. Since the description is the same as that of FIGS. 2 (b) and 2 (c), detailed description thereof will be omitted. After driving the address bus, the data bus is driven on each of the three clocks (see also third (d)).

Thereafter, an address response (see also third (e)) is received in the memory, and a data response (see also third (f)) is received in the memory.

However, in the above-described conventional memory access operation process, since a plurality of processors (1 to 1n) are operated in the system, a bus use request may be collided, and thus address arbitration before starting a bus cycle (see also second (a)). (See also Section 2 (b)) to obtain permission.

Therefore, since the address arbitration cycle uses one bus clock, but multiple processors can participate in arbitration at the same time, it is possible for any processor to take part in arbitration and get bus usage permission. The efficiency of the processors can be increased, but since several bus cycles are executed simultaneously, a problem arises that the efficiency of use of the bus is considerably increased in the system-wide aspect.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is to provide a Hi-Pi bus for minimizing the use of a bus by using a memory access request as a bus cycle while allowing a plurality of processors to operate without data collision. It is to provide a data transmission control device.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

4 is a block diagram of a data transmission control apparatus according to the present invention, which is located between each of the processors constituting the system and a hi-fi bus, wherein the processor 9 generates various data read / write cycles according to memory requirements. A data transmission controller 11 for generating a control signal, an address arbiter 12 for arbitration of an address bus by receiving a signal generated by the transmission controller 11, storing an address and control information, and using an address Upon receiving the permission, the address buffer 13 driving the address bus at a predetermined point in the bus cycle, the data buffer 14 storing data and driving the data bus at a predetermined point in the write cycle, and the data buffer 14 The address generated at the time point before the operation start of the address buffer 13 by receiving the address response at the time of operation The address response latch 15 that determines whether the switch arrived in the memory well, and the data response received at the write cycle after the operation point of the data buffer 14 are received to generate the data generated at the operation point of the address buffer 13. The data response latch 16 which determines whether the memory arrives well and the reception number of the data and the number of the transmitter which has performed the read cycle are compared to determine whether the data generated in the memory should reach itself during the read cycle operation. It consists of a comparator 17 and a data latch 18 and a parity checker 19 which receive data received in a read cycle from the bus.

The data transfer controller 11 is composed of an arbitration requester 111, an address buffer controller 112, a data controller 113, and a cycle terminator 114, as shown in FIG.

The arbitration requester 111 receives the preq signal of the microprocessor 9 and the address bus permission signal Win of the address arbiter 12 and uses the address bus when the state of the preq signal is "1". The address arbitration start signal areq signal is kept at " 1 " state until the permission signal win becomes " 1 ".

In addition, the address buffer controller 112 receives the address bus permission signal win of the address arbiter 12 and the address signal addr of the microprocessor 9 to receive the address bus permission signal ( When win is in the " 1 " state, the address bus drive signal aoe is output as " 1 " while the address signal addr is output.

The data controller 113 also includes an address bus driving signal aoe output from the address buffer controller 112, an aok signal of the address response latch 15, an arrival signal of the comparator 17 and the microprocessor ( Prw signal and data signal generated in 9) are inputted.

At this time, the operation of the data controller 113 is the state of the doe signal if the state of the Prw signal is "0", that is, the write and the state of the address bus drive signal (aoe) signal is "1", that is, the bus is available. Change to "1" and output the data.

If the state of the prw signal is " 1 ", that is, a read and the state of the address bus drive signal aoe signal is " 1 ", that is, a bus use function, the state of the dlatch signal is output as " 1 ".

The dlatch signal continues until the state of the arrived signal is input to "1".

In addition, the cycle finisher 114 receives the arrived signal of the comparator 17, the dok signal of the data response latch 16, and the dperr signal of the parity checker 19.

The operation of the cycle terminator 114 is determined by a system error when the state of the arrived signal of the input signal is "1" and the state of the dperr signal is "1". 9) to transmit.

In addition, if the state of the dok signal of the data response latch 16 of the input signal is "1", the cycle terminator 114 converts the state of the done signal to "1" and transmits it to the microprocessor 9.

A preferred operation example of a data transmission control apparatus of a HiPi bus according to the present invention configured as described above will be described according to the operation flowchart shown in FIG. 6 and FIG. Reference is made to the example signal waveforms shown in FIG. 6 is a flowchart of a data transmission control of the data transmitter 11. In step S101, the arbitration requester 111 of the data transmitter 11 checks the signal state of preq output from the microprocessor 9.

If it is determined in step S101 that the state of the preq signal is " 1 ", the flow advances to step S102 to switch the address arbitration start signal areq signal to " 1 ".

The address arbitration start signal areq signal output in step S102 is input to the address arbiter 12.

At this time, the address arbiter 12 receiving the address arbitration start signal (areq) signal of the high state drives the arbitration signal ABREQ to the high state and all of the system including its arbitration signal line ABREQ. Read the arbitration signal line of the arbitrator and wait until his or her arbitration request has the highest priority.

Subsequently, when the arbitration request has the highest priority, the address arbiter 12 transmits the permission signal win of the address bus to the arbitration requester 111 and transmits its arbitration signal ABREQ. Switch to 0 "state.

When the permission signal win is input to the arbitration requester 111 in a state of "1", the address arbitration start signal areq signal is switched to "0".

The permission signal win generated by the address arbiter 12 is also input to the address buffer controller 112. The address buffer controller 112 checks the state of the permission signal win in step S103. If 1 ", the process proceeds to step S104. If" 0 ", the process proceeds to the step S102 again, and the above-described process is performed again.

The address buffer controller 112, which has received address data and control data generated by the microprocessor 9 and stores them in the address buffer 13, sends an address bus drive signal aoe for data transfer in step S104. After one bus clock (see section T2 in FIG. 5 of the accompanying drawings) is transferred to the address buffer 13 in a high state, the process proceeds to step S105.

In step S105, the data controller 113 checks the Prw signal output from the microprocessor 9, and proceeds to step S106 if the Prw is " 1 "

If the Prw checked in step S105 is " 0 ", that is, write, the flow proceeds to step S112. Step S106 proceeds to step S107 after maintaining the standby state for a predetermined time. In step S107, the aklatch is outputted to 1 and then the procedure goes to step S108.

In step S108, the aok signal output from the address response latch 15 is examined. If the aok signal is " 1 ", the process proceeds to step S109. If the aok signal " 0 " checked in step S108, the flow advances to step S117.

In step S109, the arrival output signal of the comparator 17 is checked, and if the arrival is "1", the flow proceeds to step S110.

In step S110, the dlatch is driven to " 1 ", data is input, and the flow proceeds to step S111.

In step S111, the dperr output signal of the parity checker 19 is inspected. If the dperr output signal is "1", that is, an error goes to step S177, while "0", that is, there is no error, goes to step S118. do. In step S112, the doe signal is output as "1", the data is output, and the flow proceeds to step S113.

In step S113, aklatch is output as "1", and the flow proceeds to step S114. In step S114, the dok signal of the data response latch 16 is input and checked.

At this time, if the dok signal is "0", the processing proceeds to step S117, and if "1", the processing proceeds to step S118.

In the above-described process, step S117 outputs an error signal to the microprocessor 9 as "1" and ends the corresponding control function.

In addition, the step S118 outputs the done signal as "1" in the microprocessor 9 and ends the control process. 7 is a flowchart of an address arbitration control of the address arbiter 12. In step S201, the areq signal of the data transfer controller 11 is checked.

If the areq signal is "1" in step S201, the flow advances to step S202, and the areq signal waits in step S "0" step S201. In step S202, the ABREQ [N] is outputted as "1" to the HiPi bus 20, and the flow proceeds to step S203.

ABREQ [N] is one of the arbitration signal lines ABREQ [12: 0] composed of 13 signals, and N has a value between 0 and 12. In step 203, the ABREQ [12: 0] signal line of the HiPi bus 20 is examined.

Examine the values of all signals between ABREQ [12] and ABREQ [N + 1], and if all are 0, proceed to step S204. If any signal between ABREQ [12] and ABREQ [N + 1] is "1", ", It progresses to the said step S202. In step S204, the ABREQ [N] is outputted as "0", the win signal is outputted as "1" to the data transmitter 11, and then the control operation is terminated.

By providing a data transfer control apparatus of a HiPi bus according to the present invention operating as described above it is possible to efficiently use the occupancy time of the shared bus.

Claims (1)

In a system of a shared bus multiprocessor in which a plurality of microprocessors (9) and a plurality of memories are connected to a hi-fi bus (20), each processor constituting a system and a hi-fi bus are located between the processors and the processor (9) is a memory request. A data transfer controller 11 for generating various control signals for generating a data read / write cycle according to the present invention; An address arbiter (12) for receiving a signal generated by the transmission controller (11) to arbitrate an address bus; An address buffer 13 for storing the address and control information and driving the address bus at a predetermined point in the bus cycle upon receiving the address permission; A data buffer 14 for storing data and driving the data bus at a predetermined point in the write cycle; An address response latch (15) for receiving an address response at an operation point of the data buffer (14) and determining whether an address generated at the point before the operation of the address buffer (13) arrives in the corresponding memory well; A data response latch (16) for receiving a data response in a write cycle after an operation point of the data buffer (14) to determine whether data generated at the operation point of the address buffer (13) arrives well in memory; A comparator 17 for comparing the reception number of the data with the number of the transmitter that has performed the read cycle to determine whether data generated in the memory should reach its own during the read cycle operation; And a data latch (18) and a parity checker (19) for receiving data received in a read cycle from the bus.