KR950007118B1 - Display control circuit for hardware cursor - Google Patents

Abstract

The circuit can diversely control blink speed when a hardware cursor is displayed on a monitor and can freely select a cursor size as bit unit. It comprises : (i) a CRT control circuit unit(1) generating a horizontal/vertical synchronization signal and a display signal; (ii) a cursor generating circuit unit(2) generating a cursor signal; (iii) a blink control circuit unit(3) generating a blink signal according to a blink data value; and (iv) a data selection circuit unit(4) that selects a memory data or a cursor color data and transmits it to the monitor.

Description

Display control circuit of hardware cursor

1 is a block diagram of a display control circuit of the hardware cursor of the present invention.

2 is a detailed block diagram of the cursor generation circuit unit of FIG.

3 is a detailed block diagram of the blink control circuit of FIG.

4 is a detailed configuration diagram of the data selection circuit section of FIG.

5 is an explanatory diagram showing a method of generating a cursor signal according to the present invention.

* Explanation of symbols for main parts of the drawings

1: cathode ray and control circuit part 2: cursor generation circuit part

3: blink control circuit portion 4: data selection circuit portion

21: horizontal counter 22: vertical counter

23: comparison operator 31: clock divider

32: loading counter 33: signal combiner

41: AND operator 42: multiplexer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cursor that appears on a monitor. In particular, when a hardware cursor is to be displayed on a monitor, the speed of the blink can be controlled in various ways. It relates to a control circuit.

Conventionally, the size of a cursor has been fixed in character cells, and there is a problem that a lot of restrictions are placed on the selection of the blink rate.

In view of such a conventional problem, the present invention is characterized by controlling the size and speed of the cursor displayed on the monitor.

That is, in displaying a hardware cursor on a monitor, the position of the cursor can be determined in bits, the size of the cursor can be expressed in bits, and the blinking blink speed of the cursor can be varied.

When described in detail with reference to the drawings as follows.

The display control circuit of the hardware cursor of the present invention includes a cathode ray tube control circuit section 1 for generating a horizontal / vertical synchronization signal and a display signal for controlling the display of the monitor, as shown in FIG. A cursor generation circuit section 2 for generating a cursor signal by using the horizontal and vertical synchronization signals generated by the cathode ray tube control circuit section 1 as a clock; A blink control circuit section (3) for generating a blink signal according to the blink data value inputted as a clock to the vertical synchronizing signal generated by the cathode ray tube control circuit section (1); And a data selection circuit section 4 which selects memory data or cursor color data inputted by the output of the cursor generation circuit section 2 and the blink control circuit section 3 and transmits them to the monitor.

As shown in FIG. 2, the cursor generation circuit section 2 includes: a horizontal counter 21 for generating a horizontal address in units of bits by a pixel clock in a horizontal display area; A vertical counter 22 for generating a vertical address in units of bits in a vertical display area with a clock of a horizontal synchronization signal representing a unit of lines; Comparing arithmetic unit 23 for generating a cursor signal by comparing the address generated by the horizontal counter 21 and the vertical counter 22 with the set cursor information.

The blink control circuit section 3 includes a clock divider 31 for dividing by using a vertical display signal as a clock as shown in FIG. A loading counter 32 which receives the blink data value set in synchronization with the clock divided by the clock divider 31 and repeats the counting; The signal combiner 33 generates a blink signal for controlling the address generated by the loading counter 32.

As shown in FIG. 4, the data selection circuit section 4 includes an AND operator 41 for performing an AND operation on the input blink signal and the cursor signal; The output of this end operator 41 is configured by a multiplexer 42 which displays cursor color data or memory data on a monitor.

Referring to the operation and effects of the present invention configured as described above in detail.

Using the horizontal synchronizing signal H-SYNC and the vertical synchronizing signal V-SYNC generated by the cathode ray tube control circuit unit 1 as a clock, the cursor generation circuit unit 2 generates a cursor signal, and the blink control circuit unit 3 ) Uses the vertical synchronization signal (V-SYNC) that is the screen unit as a clock to generate an appropriate blink signal according to the input blink data value.

The two signals generated in this way transmit the cursor color data to the monitor when the blink and the cursor are active in the data selection circuit section 4, while the memory data is transferred when the signal of either of the two signals is inactivated to display the monitor screen. It will be refreshed.

Here, the operation will be described as follows.

First, referring to the detailed operation of the cursor generation circuit unit 2, the horizontal counter 21 generates a horizontal address in bits by the pixel clock in the horizontal display signal (H-DISP) area, and thereafter, a column of the cursor. It is input to the comparator 23 to indicate the position and size, and the vertical counter 22 uses the horizontal synchronizing signal H-SYNC, which can represent a line unit, as a clock to display the vertical display signal V-DISP. In the () region, a bitwise vertical address is generated and input to the comparator 23 to indicate the row position and size of the cursor.

The comparison operator 23 sets the set cursor information, that is, the cursor width (referred to as CW below Cursor Width), the cursor height (referred to as CH below Cursor Height), the cursor horizontal position (referred to as CHP below Cursor Horizontal Position), and the cursor vertical position. As shown in FIG. 5, the value of (Cursor Vertical Position hereinafter referred to as CVP) and the horizontal address and vertical address generated by the horizontal counter 21 and the vertical counter 22 are compared to set the information area 2A. Will generate a cursor signal.

At this time, the cursor information input to the comparator 23, that is, the values of the cursor width CW, the cursor height CH, the cursor horizontal CHP, and the cursor vertical position CVP, are designed as registers. Likewise, data can be input / output using the input / output port of a central processing unit (not shown).

Meanwhile, the blink control circuit unit 3 uses the vertical display signal V-DISP, which means a screen unit, as the clock for generating the clink signal, and divides the basic clock into four divisions to 16 in the clock divider 31. Dispensing is performed appropriately by dividing, and it supplies to the clock of the loading counter 32.

Here, the frequency division is necessary because the vertical display signal V-DISP is generated more than 60 times per second, so it is efficient to use the frequency division appropriately.

In this way, the loading counter 32 receiving the divided clock receives the set blink data value and repeats the count.

The signal combiner 33 controls the address generated by the loading counter 32 to generate a blink signal, and when the count value of the loading counter 32 reaches zero, loading the blink data again is repeated. A "reload" signal is applied to the loading counter 32 so that the blink signal alternately appears.

In addition, when the enable signal of the signal combiner 33 is high, the enable signal is a signal that makes the enhancement signal high. Table 1 shows the generation of such a signal.

TABLE 1

The data selection circuit section 4 which selects the cursor color data using the blink and cursor signals generated in the above-described manner is a multiplexer if both the blink and the cursor input to the AND operator 41 are high. In step 42), the cursor color data is selected to be displayed on the monitor. Otherwise, the screen memory data accessed from the memory can be selected and displayed by the multiplexer 42.

As described in detail above, in the present invention, in displaying a hardware cursor on a monitor, the position and size of the cursor can be variously controlled and selected in units of bits, and the speed of the cursor blink can be freely selected. There is an effect to improve the performance and applicability.

Claims (4)

A cathode ray tube control circuit section 1 for generating a horizontal / vertical synchronization signal and a display signal to control the display of the monitor; A cursor generation circuit section 2 for generating a cursor signal by using the horizontal and vertical synchronization signals generated by the cathode ray tube control circuit section 1 as a clock; A blink control circuit section (3) for generating a blink signal according to the blink data value inputted as a clock to the vertical synchronizing signal generated by the cathode ray tube control circuit section (1); And a data selection circuit section 4 for selecting the memory data or the cursor color data inputted by the output of the cursor generating circuit section 2 and the blink control circuit section 3 and transmitting them to the monitor. Display control circuit. 2. The apparatus of claim 1, wherein the cursor generation circuit section (2) comprises: a horizontal counter (21) for generating a horizontal address in units of bits by a pixel clock in a horizontal display area; A vertical counter 22 for generating a vertical address in units of bits in a vertical display area with a clock of a horizontal synchronization signal representing a unit of lines; And a comparator (23) for generating a cursor signal by comparing the addresses generated by the horizontal counter (21) and the vertical counter (22) with the set cursor information. 2. The apparatus of claim 1, wherein the blink control circuit section (3) comprises: a clock divider (31) for dividing by using a vertical display signal as a clock; A loading counter 32 which receives the blink data value set in synchronization with the clock divided by the clock divider 31 and repeats the counting; And a signal combiner (33) for controlling the address generated by the loading counter (32) to generate a blink signal. 2. The data selection circuit (4) according to claim 1, further comprising: an AND operator (41) for performing an AND operation on the input signal and the cursor signal; And a multiplexer (42) for displaying cursor color data or memory data on a monitor by the output of the AND operator (41).