KR950006602A - Memory access device and memory access method - Google Patents

Memory access device and memory access method Download PDF

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Publication number
KR950006602A
KR950006602A KR1019940019730A KR19940019730A KR950006602A KR 950006602 A KR950006602 A KR 950006602A KR 1019940019730 A KR1019940019730 A KR 1019940019730A KR 19940019730 A KR19940019730 A KR 19940019730A KR 950006602 A KR950006602 A KR 950006602A
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KR
South Korea
Prior art keywords
address
record
memory
buffer memory
ring buffer
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KR1019940019730A
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Korean (ko)
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KR970001918B1 (en
Inventor
마사미치 사카이노
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츠지 요시후미
닛산 지도유샤 가부시키가이샤
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Publication of KR950006602A publication Critical patent/KR950006602A/en
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646Configuration or reconfiguration
    • G06F12/0669Configuration or reconfiguration with decentralised address assignment
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0638Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module

Abstract

본 발명은 MPU의 메모리엑세스시의 부하를 경감하고, 다량의 메모리엑세스 또는 고속의 메모리엑세스를 가능하게 한다.The present invention reduces the load on the memory access of the MPU, and enables a large amount of memory access or a high speed memory access.

논리링버퍼메모래의 어드레스인 버퍼링어드레스데이타 및 레코드어드레스데이타는, MPU내의 레코드포인터로 할당된다. 목적의 논리링버퍼메모리의 어드레스로의 엑세스는, 이 레코드포인트로부터 MPU내부의 처리단계수가 많은 제산명령을 사용하지 않고 하드웨어 혹은 소프트웨어에 의해 어드레스가 연산되며 행해진다. 이 때문에, 논리링버퍼메모리로의 엑세스시간은 단축된다. 따라서 본 발명에 의하면, 아무리 처리능력이 낮은 MPU라도 다량의 데이터를 고속으로 엑세스할 수가 있다.The buffering address data and the record address data, which are addresses of the logical ring buffer memory, are allocated to the record pointers in the MPU. Access to the address of the target logical ring buffer memory is performed from the record point by calculating the address by hardware or software without using a divide instruction having a large number of processing steps in the MPU. For this reason, the access time to the logical ring buffer memory is shortened. Therefore, according to the present invention, a large amount of data can be accessed at high speed even with a low MPU.

Description

메모리 엑세스장치 및 메모리 엑세스방법Memory access device and memory access method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 일실시예인 메모리 엑세스장치의 개략을 보인 구성도.3 is a block diagram showing an outline of a memory access device according to an embodiment of the present invention.

제4도는 본 발명의 메모리 엑세스방법의 순서를 설명하기 위한 흐름도.4 is a flow chart for explaining the procedure of the memory access method of the present invention.

내용 없음No content

Claims (3)

메모리가 복수의 뱅크로 분할되고, 해당 뱅크는 또한 복수의 레코드로 분할된 구성을 갖고, 연속된 링모양으로 가상되는 논리링버퍼메모리에, 데이타를 엑세스하는 메모리 엑세스방법에 있어서, 상기 논리링버퍼메모리의 어드레스인 뱅크어드레스 및 레코드어드레스를 격납하는 레코드 포인터를 설치하고, 해당 레코드포인터로부터 상기 논리링버퍼메모리의 어드레스를 제산처리하지 않고 구하며, 해당 구한 상기 논리링버퍼메모리의 어드레스를 엑세스하는 것을 특징으로 하는 메모리 엑세스방법.A memory access method for accessing data in a logical ring buffer memory in which a memory is divided into a plurality of banks, and the bank is also divided into a plurality of records and is virtualized in a continuous ring shape. A record pointer for storing a bank address and a record address, which are addresses of a memory, is provided, the record pointer is obtained without dividing the address of the logical ring buffer memory from the record pointer, and the address of the logical ring buffer memory obtained is accessed. Memory access method. 메모리가 복수의 뱅크로 분할되고, 해당 뱅크는 또한 복수의 레코드로 분할된 구성을 갖고, 연속된 링모양으로 가상되는 논리링버퍼메모리에 데이터를 엑세스하는 메모리 엑세스방법으로, 뱅크어드레스데이타 및 레코드어드레스데이타를 격납하는 레코드포인터를 설치하고, 해당 레코드포인터를 쉬프트하고 상기 뱅크어드레스데이타로 하고, 상기 레코드포인터를 마크하고 상기 레코드어드레스데이타로 하고, 상기 뱅크어드레스데이타로 상기 논리링버퍼메모리의 뱅크오프셋값을 가산하고 뱅크어드레스를 구하고, 상기 레코드어드레스데이타에 한 개의 레코드의 최대바이트수를 승산하고 논리링버퍼메모리의 레코드 오프셋값을 가산하고 레코드어드레스를 구하고, 상기 연산한 상기 뱅크어드레스 및 상기 레코드어드레스에 해당하는 상기 논리링버퍼메모리의 어드레스를 엑세스하는 것을 특징으로 하는 메모리 엑세스방법.A memory access method in which a memory is divided into a plurality of banks, and the bank is also divided into a plurality of records and accesses data to a logical ring buffer memory virtualized in a continuous ring form. A record pointer for storing data is provided, the record pointer is shifted to the bank address data, the record pointer is marked, the record address data is used, and the bank address data is used as the bank offset value of the logical ring buffer memory. , Add a bank address, multiply the maximum number of bytes of one record to the record address data, add a record offset value of a logical ring buffer memory, obtain a record address, and add the calculated address to the computed bank address and the record address. Corresponding logic ring A memory access method comprising accessing an address of a buffer memory. 메모리가 복수의 뱅크로 분할되고, 해당 뱅크는 또한 복수의 레코드로 분할된 구성을 갖고, 연속된 링모양으로 가상되는 논리링버퍼메모리에 데이타를 엑세스하는 메모리 엑세스장치로, 데이타를 읽어 내고 또 데이터를 기입하기 위해 상기 논리링버퍼메모리에 엑세스를 행하는 연산처리수단과, 해당 연산처리수단으로부터의 뱅크어드레스메모리데이타를 가산하고 목적의 상기 논리링버퍼메모리의 뱅브어드레스를 연산하눈 제1가산수단과, 해당 제1가산수단에 의해 연산된 뱅크 어드레스에 따라서 상기 논리링버퍼메모리의 뱅크를 선택하는 선택수단과, 상기 연산수단으로부터의 레코드어드레스데이타에 한 개의 레코드의 최대바이트수를 승산하는 승산수단과, 해당승산수단에 의새 승산된 데이터 및 상기 연산처리수단으로부터의 상기 논리링버퍼메모리의 레코드오프셋값을 가산하고 상기 논리링버퍼메모리의 어드레스를 연산하고 선택하는 제2가산수단을 갖는 것을 특징으로 하는 메모리 엑세스 장치.The memory is divided into a plurality of banks, which bank is also divided into a plurality of records, and is a memory access device that accesses data in a logical ring buffer memory that is virtualized in a continuous ring shape. An arithmetic processing means for accessing the logical ring buffer memory to write a first, first adding means for adding a bank address memory data from the arithmetic processing means and calculating a bang address of the logical ring buffer memory of interest; Selecting means for selecting a bank of the logical ring buffer memory in accordance with the bank address calculated by the first adding means, multiplication means for multiplying the record address data from the computing means by a maximum number of bytes of one record; Data newly multiplied by the multiplication means and the logical linker from the calculation processing means. Adding the record offset value in memory and memory access apparatus characterized in that it has a second addition means for computing, and selecting an address of the logical ring buffer memory. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR94019730A 1993-08-10 1994-08-10 Memory access apparatus and its method KR970001918B1 (en)

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JP93-198433 1993-08-10
JP5198433A JP3042266B2 (en) 1993-08-10 1993-08-10 Memory access method

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KR950006602A true KR950006602A (en) 1995-03-21
KR970001918B1 KR970001918B1 (en) 1997-02-19

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970066894A (en) * 1996-03-08 1997-10-13 김광호 High-speed data access method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006260411A (en) * 2005-03-18 2006-09-28 Japan Radio Co Ltd Signal processor, and communication equipment using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970066894A (en) * 1996-03-08 1997-10-13 김광호 High-speed data access method

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JP3042266B2 (en) 2000-05-15
JPH0756805A (en) 1995-03-03
KR970001918B1 (en) 1997-02-19

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