KR950006598A - How to design variable length code - Google Patents

How to design variable length code Download PDF

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Publication number
KR950006598A
KR950006598A KR1019930015192A KR930015192A KR950006598A KR 950006598 A KR950006598 A KR 950006598A KR 1019930015192 A KR1019930015192 A KR 1019930015192A KR 930015192 A KR930015192 A KR 930015192A KR 950006598 A KR950006598 A KR 950006598A
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KR
South Korea
Prior art keywords
length code
code
variable length
sets
error
Prior art date
Application number
KR1019930015192A
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Korean (ko)
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KR950010424B1 (en
Inventor
김상호
Original Assignee
배순훈
대우전자 주식회사
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Priority to KR1019930015192A priority Critical patent/KR950010424B1/en
Publication of KR950006598A publication Critical patent/KR950006598A/en
Application granted granted Critical
Publication of KR950010424B1 publication Critical patent/KR950010424B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/40—Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2903—Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
    • H04N19/91—Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

본 발명은 채널 전송시 비트 에러에 강한 VLC디자인방법에 관한 것이므로, 전체 사건들을 여러개의 집합으로 묶는 스텝과, 집합들에 대한 코드를 디자인하는 스텝과, 에러 정정기법을 사용하여 패리티 비트를 첨가하는 스텝과, 각 집합내의 원소들에 대한 코드를 디자인하는 스텝과, 집합들에 대한 코드와 패리티 비트 및 각 집합내의 원소들에 대한 코드를 합쳐 각 원소에 대한 VLC코드로 하는 스텝으로 구성되어, 적은 수의 패리티 비트로 에러정정을 수행하고, 에러 정정을 할 수 없는 부분에서 비트 에러가 생겨 다른 데이터로 복호화 되더라도 오류가 별로 띄지 않도록 하여 채널 전송 에러에 강한 내성을 가지도록 한 것이다.Since the present invention relates to a VLC design method that is resistant to bit errors in channel transmission, a step of tying the entire event into multiple sets, a step of designing a code for the sets, and adding a parity bit using an error correction technique Step, designing the code for the elements in each set, and combining the code and parity bits for the sets and the code for the elements in each set into a VLC code for each element. The error correction is performed with a number of parity bits, and a bit error occurs in the part where error correction cannot be performed, so that the error is less prominent even if it is decoded into other data, so that it has a strong resistance to channel transmission error.

Description

가변길이 코드 디자인방법How to design variable length code

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 가변길이 코드 디자인방법의 흐름도이다.1 is a flowchart of a variable length code design method according to the present invention.

내용 없음No content

Claims (2)

각 사건들에 대한 확률을 얻은 제1스텝과; 화상에 대해 비슷한 효과를 갖는 사건들을 하나의 집합으로 묶어서 여러개의 집합으로 만드는 제2스텝과; 상기 제2스텝의 각 집합들에 대해 고정 길이 코드를 디자인하는 제3스텝과; 상기 제3스텝의 고정 길이 코드에 에러 정정기법을 사용하여 패리티 비트를 첨가하는 제4스텝과; 상기 제2스텝의 각 집합내의 사건들에 대해 가변길이 코드를 디자인하는 제5스텝과; 상기 제4스텝의 고정길이 코드와 패리티 비트 및 제5스텝의 가변길이 코드를 더해서 각 사건에 대한 최종 가변길이 코드로 정하는 제6스텝으로 이루어지는 가변길이 코드 디자인방법.A first step of obtaining a probability for each event; A second step of grouping events having a similar effect on the image into one set to form a plurality of sets; A third step of designing a fixed length code for each set of said second steps; A fourth step of adding a parity bit to the fixed length code of the third step by using an error correction technique; A fifth step of designing a variable length code for the events in each set of the second step; And a sixth step of adding the fixed length code of the fourth step, the parity bit, and the variable length code of the fifth step to determine a final variable length code for each event. 제1항에 있어서, 제1스텝은, 집합의 개수가 2의 승수개인 것을 특징으로 하는 가변길이 코드 디자인 방법.The variable length code design method according to claim 1, wherein the first step is a multiplier of two sets. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930015192A 1993-08-05 1993-08-05 Design method of variable length method KR950010424B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930015192A KR950010424B1 (en) 1993-08-05 1993-08-05 Design method of variable length method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930015192A KR950010424B1 (en) 1993-08-05 1993-08-05 Design method of variable length method

Publications (2)

Publication Number Publication Date
KR950006598A true KR950006598A (en) 1995-03-21
KR950010424B1 KR950010424B1 (en) 1995-09-16

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ID=19360803

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930015192A KR950010424B1 (en) 1993-08-05 1993-08-05 Design method of variable length method

Country Status (1)

Country Link
KR (1) KR950010424B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100719743B1 (en) * 1999-12-20 2007-05-17 주식회사 케이티 Coding and decoding using reversible variable length coding

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100719743B1 (en) * 1999-12-20 2007-05-17 주식회사 케이티 Coding and decoding using reversible variable length coding

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Publication number Publication date
KR950010424B1 (en) 1995-09-16

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