KR950006588A - High Speed Computing Adder - Google Patents

High Speed Computing Adder Download PDF

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Publication number
KR950006588A
KR950006588A KR1019930016984A KR930016984A KR950006588A KR 950006588 A KR950006588 A KR 950006588A KR 1019930016984 A KR1019930016984 A KR 1019930016984A KR 930016984 A KR930016984 A KR 930016984A KR 950006588 A KR950006588 A KR 950006588A
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South Korea
Prior art keywords
carry
adding means
adder
bit group
mantissa
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KR1019930016984A
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Korean (ko)
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KR950015180B1 (en
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김성정
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배순훈
대우전자 주식회사
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Publication of KR950006588A publication Critical patent/KR950006588A/en
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Publication of KR950015180B1 publication Critical patent/KR950015180B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)

Abstract

본 발명은 고속연산형 가산기에 관한 것으로, 가산될 가수의 복수비트군으로부터 임의로 분할된 제1비트군의 가산을 수행하여 가산결과와 캐리를 출력하는 제1가산수단(50)과, 상기 분할된 가수비트군의 제2비트군에 대해 캐리유무에 대한 연산을 동시에 수행하는 복수의 가산기(51, 52)로 구성된 제2가산수단과 상기 제1가산수단의 캐리에 의해 상기 제2가산수단의 출력을 선택출력하는 멀티플렉서(53), 상기 분할된 비트군의 제3비트군에 대해 캐리유무에 대한 연산을 동시에 수행하는 복수의 가산기(54, 55)로 구성된 제3가산수단과 상기 제2가산수단의 캐리에 따라 상기 제3가산수단의 가산결과치를 선택출력하는 멀티플렉서(56)를 구비하여 구성된 것이다.The present invention relates to a fast computing type adder, comprising: first adding means (50) for performing an addition of a first bit group arbitrarily divided from a plurality of bit groups of an adder to be added, and outputting an addition result and a carry; Output of the second adding means by a second adding means comprising a plurality of adders 51 and 52 which carry out a calculation on whether a carry is performed on the second bit group of the mantissa bit group and the first adding means A third adder and a second adder comprising a multiplexer 53 for selectively outputting a plurality of adders, and a plurality of adders 54 and 55 for simultaneously performing a carry operation on the third bit group of the divided bit group. And a multiplexer 56 for selectively outputting the addition result value of the third adding means according to the carry.

Description

고속연산형 가산기High Speed Computing Adder

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명에 따른 고속연산형 가산기를 설명하는 도면.4 is a diagram for explaining a fast operation type adder according to the present invention.

제5도(a)는 제4도에 도시된 캐리“1”가산기와 캐리“0”가산기의 구성을 나타낸 도면이다.FIG. 5 (a) is a diagram showing the configuration of the carry “1” adder and carry “0” adder shown in FIG.

Claims (4)

가산될 가수의 복수비트군으로부터 임의로 분할된 제1비트군의 가산을 수행하여 가산결과와 캐리를 출력하는 제1가산수단(50)과, 상기 분할된 가수비트군의 제2비트군에 대해 캐리유무에 대한 연산을 동시에 수행하는 복수의 가산기(51,52)로 구성된 제2가산수단과 상기 제1가산수단의 캐리에 의해 상기 제2가산수단의 출력을 선택출력하는 멀티플렉서(53), 상기 분할된 비트군의 제3비트군에 대해 캐리유무에 대한 연산을 동시에 수행하는 복수의 가산기(54, 55)로 구성된 제3가산수단과 상기 제2가산수단의 캐리에 따라 상기 제3가산수단의 가산결과치를 선택출력하는 멀티플렉서(56)를 구비하여 구성된 것을 특징으로 하는 고속연산형 가산기.A first adding means (50) for performing an addition of the first bit group arbitrarily divided from the plurality of bit groups of the mantissa to be added and outputting an addition result and a carry; and a carry for the second bit group of the divided mantissa bit group A multiplexer 53 for selectively outputting the output of the second adding means by the second adding means composed of a plurality of adders 51 and 52 which simultaneously perform arithmetic operations on the presence or absence and the carry of the first adding means; The third adding means comprising a plurality of adders 54 and 55 which simultaneously perform a carry operation on the third bit group of the selected bit group and the third adding means according to the carry of the second adding means. A high speed computation type adder, comprising: a multiplexer 56 for selectively outputting result values. 제1항에 있어서, 상기 제2가산수단과 제3가산수단을 이루는 복수의 가산기중 하나는 일단이 하이레벨로 설정되는 캐리“1”가산기(51, 54)와 일단이 로우레벨로 설정된 캐리“0”가산기(52, 55)로 구성되어 할당된 비트열을 동시에 연산하도록 구성된 것을 특징으로 하는 고속연산형 가산기.The carry-on apparatus of claim 1, wherein one of the plurality of adders constituting the second adding means and the third adding means has a carry " 1 " adder 51 and 54 whose one end is set to a high level and a carry " A fast computing type adder, comprising: 0 ”adders (52, 55) configured to simultaneously calculate the assigned bit strings. 제2항에 있어서, 상기 캐리“1”가산기는 상기 가산될 가수의 가산치(Ci)를 AND처리하여 캐리(Ci+1)를 얻는 AND게이트(62)로 구성된 것을 특징으로 하는 고속연산형 가산기.3. The fast operation adder as set forth in claim 2, wherein the carry "1" adder is composed of an AND gate 62 which ANDs the addition value Ci of the mantissa to be added to obtain a carry Ci + 1. . 제2항에 있어서, 상기 캐리“0”가산기는 가수(Ai), (Bi)의 가산치(Pi)를 얻는 배타화 논리게이트(71)와, 이 배타화 논리게이트(71)의 출력(Pi)를 반전시켜 최종 정상치(Si)를 얻는 인버터(72), 상기 가수(Ai)와 피가수(Bi)를 AND처리하는 AND게이트(73)와, 이 AND게이트(73)에 의한 AND처리결과 (Gi)와 상기 출력(Pi)를 OR처리하여 캐리C(i+1)를 생성하는 OR게이트(74)로 구성된 것을 특징으로 하는 고속연산형 가산기.The carry "0" adder includes an exclusion logic gate 71 for obtaining addition values Pi of mantissa Ai and Bi, and an output Pi of the exclusion logic gate 71. Inverter 72 obtains the final normal value Si by inverting?, An AND gate 73 for ANDing the mantissa Ai and the surplus singer Bi, and an AND processing result (Gi) by the AND gate 73 And OR gate (74) for ORing the output (Pi) to generate carry C (i + 1). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930016984A 1993-08-30 1993-08-30 High speed adder KR950015180B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100339245B1 (en) * 1998-12-22 2002-07-18 박종섭 Adder

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100339245B1 (en) * 1998-12-22 2002-07-18 박종섭 Adder

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